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    <title>topic Re: Coreboot + FSP for Tigerlake in Embedded Intel® Core™ Processors</title>
    <link>https://community.intel.com/t5/Embedded-Intel-Core-Processors/Coreboot-FSP-for-Tigerlake/m-p/1450658#M4417</link>
    <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/114"&gt;@CarlosAM_INTEL&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;
&lt;P&gt;Apologies for the incomplete information provided.&lt;/P&gt;
&lt;P&gt;&lt;BR /&gt;Q: Could you please clarify if this request is related to a Tiger Lake design developed by you or a design developed by a third-party company? &lt;BR /&gt;A: This is regarding the design developed by Intel TigerLake-UP3 RVP (QDF# QXLC)&lt;/P&gt;
&lt;P&gt;Q: Please let us know the part number of the processor.&lt;BR /&gt;A: i7-1195G7&lt;/P&gt;
&lt;P&gt;Q: What is the name of the manufacturer, the part number, and where we can find the information if this request is related to a third-party design?&lt;BR /&gt;A: Intel RVP (QDF# QXLC)&lt;/P&gt;
&lt;P&gt;Q: Could you please let us know the Operating System (OS) related to this situation and its version?&lt;BR /&gt;A: Linux Ubuntu 20.04&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Thanks and Regards,&lt;/P&gt;
&lt;P&gt;&lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/272824"&gt;@Renuka18&lt;/a&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Fri, 27 Jan 2023 07:23:08 GMT</pubDate>
    <dc:creator>Renuka18</dc:creator>
    <dc:date>2023-01-27T07:23:08Z</dc:date>
    <item>
      <title>Coreboot + FSP for Tigerlake</title>
      <link>https://community.intel.com/t5/Embedded-Intel-Core-Processors/Coreboot-FSP-for-Tigerlake/m-p/1449583#M4402</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;
&lt;P&gt;Needed help regarding Coreboot FSP integration.&lt;/P&gt;
&lt;P&gt;Can you please provide any document for building coreboot along with FSP for TigerLake processor board?&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Regrads,&lt;/P&gt;
&lt;P&gt;Renuka&lt;/P&gt;</description>
      <pubDate>Tue, 24 Jan 2023 11:28:39 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Intel-Core-Processors/Coreboot-FSP-for-Tigerlake/m-p/1449583#M4402</guid>
      <dc:creator>Renuka18</dc:creator>
      <dc:date>2023-01-24T11:28:39Z</dc:date>
    </item>
    <item>
      <title>Re: Coreboot + FSP for Tigerlake</title>
      <link>https://community.intel.com/t5/Embedded-Intel-Core-Processors/Coreboot-FSP-for-Tigerlake/m-p/1449614#M4404</link>
      <description>&lt;P&gt;Hello,&amp;nbsp;&lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/272824"&gt;@Renuka18&lt;/a&gt;:&lt;/P&gt;
&lt;P&gt;Thank you for contacting Intel Embedded Community.&lt;/P&gt;
&lt;P&gt;You may find as a reference the requested information on the following website:&lt;/P&gt;
&lt;P&gt;&lt;A href="https://github.com/coreboot/fsp/tree/master/TigerLakeFspBinPkg" target="_blank"&gt;https://github.com/coreboot/fsp/tree/master/TigerLakeFspBinPkg&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;In case you have questions related to this information you should address them through the channels mentioned as a reference as well on the following website:&lt;/P&gt;
&lt;P&gt;&lt;A href="https://github.com/coreboot/fsp/pulls" target="_blank"&gt;https://github.com/coreboot/fsp/pulls&lt;/A&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Best regards,&lt;/P&gt;
&lt;P&gt;&lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/114"&gt;@CarlosAM_INTEL&lt;/a&gt;.&lt;/P&gt;</description>
      <pubDate>Tue, 24 Jan 2023 13:46:33 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Intel-Core-Processors/Coreboot-FSP-for-Tigerlake/m-p/1449614#M4404</guid>
      <dc:creator>CarlosAM_INTEL</dc:creator>
      <dc:date>2023-01-24T13:46:33Z</dc:date>
    </item>
    <item>
      <title>Re: Coreboot + FSP for Tigerlake</title>
      <link>https://community.intel.com/t5/Embedded-Intel-Core-Processors/Coreboot-FSP-for-Tigerlake/m-p/1449881#M4407</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/114"&gt;@CarlosAM_INTEL&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;
&lt;P&gt;Thank you for your time and help.&lt;/P&gt;
&lt;P&gt;It would be of great help if you could provide any document specifying how to integrate FSP into coreboot for TGL board.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Thanks and Regards,&lt;/P&gt;
&lt;P&gt;&lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/272824"&gt;@Renuka18&lt;/a&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 25 Jan 2023 05:43:22 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Intel-Core-Processors/Coreboot-FSP-for-Tigerlake/m-p/1449881#M4407</guid>
      <dc:creator>Renuka18</dc:creator>
      <dc:date>2023-01-25T05:43:22Z</dc:date>
    </item>
    <item>
      <title>Re: Coreboot + FSP for Tigerlake</title>
      <link>https://community.intel.com/t5/Embedded-Intel-Core-Processors/Coreboot-FSP-for-Tigerlake/m-p/1449922#M4409</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/114"&gt;@CarlosAM_INTEL&lt;/a&gt;&amp;nbsp;.&lt;/P&gt;
&lt;P&gt;Like for coreboot with fsp for elkhart lake, there is document number&amp;nbsp;749058.&lt;/P&gt;
&lt;P&gt;Similarly, is there any document for tigerlake?&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Thanks and Regards,&lt;/P&gt;
&lt;P&gt;&lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/272824"&gt;@Renuka18&lt;/a&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 25 Jan 2023 08:21:39 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Intel-Core-Processors/Coreboot-FSP-for-Tigerlake/m-p/1449922#M4409</guid>
      <dc:creator>Renuka18</dc:creator>
      <dc:date>2023-01-25T08:21:39Z</dc:date>
    </item>
    <item>
      <title>Re: Coreboot + FSP for Tigerlake</title>
      <link>https://community.intel.com/t5/Embedded-Intel-Core-Processors/Coreboot-FSP-for-Tigerlake/m-p/1449984#M4411</link>
      <description>&lt;P class="sub_section_element_selectors"&gt;Hello,&amp;nbsp;&lt;SPAN class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/272824"&gt;@Renuka18&lt;/a&gt;:&lt;/SPAN&gt;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;Thanks for your replies.&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;We want to address the following questions to understand this situation:&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;Could you please clarify if this request is related to a Tiger Lake design developed by you or a design developed by a third-party company? Please let us know the part number of the processor.&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;What is the name of the manufacturer, the part number, and where we can find the information if this request is related to a&amp;nbsp;third-party design?&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;Could you please let us know the Operating System (OS) related to this situation and its version?&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;Is this situation related to the following thread?&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&lt;A href="https://community.intel.com/t5/Embedded-Intel-Core-Processors/EDK-II-Setup-for-Tigerlake-Processor/m-p/1447075#M4390" target="_blank" rel="noopener"&gt;https://community.intel.com/t5/Embedded-Intel-Core-Processors/EDK-II-Setup-for-Tigerlake-Processor/m-p/1447075#M4390&lt;/A&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;We are waiting for your answer.&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;Best regards,&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&lt;A class="sub_section_element_selectors" href="https://community.intel.com/t5/user/viewprofilepage/user-id/114?emcs_t=S2h8ZW1haWx8dG9waWNfc3Vic2NyaXB0aW9ufExDVUpRTDE3RktCWFRGfDE0NDY0Mzh8U1VCU0NSSVBUSU9OU3xoSw" target="_blank" rel="noopener"&gt;@CarlosAM_INTEL&lt;/A&gt;.&lt;/P&gt;</description>
      <pubDate>Wed, 25 Jan 2023 13:28:41 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Intel-Core-Processors/Coreboot-FSP-for-Tigerlake/m-p/1449984#M4411</guid>
      <dc:creator>CarlosAM_INTEL</dc:creator>
      <dc:date>2023-01-25T13:28:41Z</dc:date>
    </item>
    <item>
      <title>Re: Coreboot + FSP for Tigerlake</title>
      <link>https://community.intel.com/t5/Embedded-Intel-Core-Processors/Coreboot-FSP-for-Tigerlake/m-p/1450236#M4413</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/114"&gt;@CarlosAM_INTEL&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;
&lt;P&gt;We are using Intel&amp;nbsp;TigerLake U DDR4 SODIMM RVP board having&amp;nbsp;11th Gen Intel (R) Core (TM)&amp;nbsp;i7-1195G7 processor.&lt;/P&gt;
&lt;P&gt;Operating System is Linux Ubuntu 20.04.&lt;/P&gt;
&lt;P&gt;Regarding the thread, both issues are regarding the same board but not the same. That thread is for EDK-II setup and this one for fsp integration with coreboot.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Thanks and Regards,&lt;/P&gt;
&lt;P&gt;&lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/272824"&gt;@Renuka18&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 26 Jan 2023 03:37:56 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Intel-Core-Processors/Coreboot-FSP-for-Tigerlake/m-p/1450236#M4413</guid>
      <dc:creator>Renuka18</dc:creator>
      <dc:date>2023-01-26T03:37:56Z</dc:date>
    </item>
    <item>
      <title>Re: Coreboot + FSP for Tigerlake</title>
      <link>https://community.intel.com/t5/Embedded-Intel-Core-Processors/Coreboot-FSP-for-Tigerlake/m-p/1450344#M4415</link>
      <description>&lt;P&gt;Hello,&amp;nbsp;&lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/272824"&gt;@Renuka18&lt;/a&gt;:&lt;/P&gt;
&lt;P&gt;Thanks for your answer.&lt;/P&gt;
&lt;P&gt;However, you still did not answer our second question and partially the first question stated in our previous message.&lt;/P&gt;
&lt;P&gt;Could you please provide the information requested in the cited questions?&lt;/P&gt;
&lt;P&gt;Thanks in advance for your reply.&lt;/P&gt;
&lt;P&gt;Best regards,&lt;/P&gt;
&lt;P&gt;&lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/114"&gt;@CarlosAM_INTEL&lt;/a&gt;.&lt;/P&gt;</description>
      <pubDate>Thu, 26 Jan 2023 13:37:08 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Intel-Core-Processors/Coreboot-FSP-for-Tigerlake/m-p/1450344#M4415</guid>
      <dc:creator>CarlosAM_INTEL</dc:creator>
      <dc:date>2023-01-26T13:37:08Z</dc:date>
    </item>
    <item>
      <title>Re: Coreboot + FSP for Tigerlake</title>
      <link>https://community.intel.com/t5/Embedded-Intel-Core-Processors/Coreboot-FSP-for-Tigerlake/m-p/1450658#M4417</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/114"&gt;@CarlosAM_INTEL&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;
&lt;P&gt;Apologies for the incomplete information provided.&lt;/P&gt;
&lt;P&gt;&lt;BR /&gt;Q: Could you please clarify if this request is related to a Tiger Lake design developed by you or a design developed by a third-party company? &lt;BR /&gt;A: This is regarding the design developed by Intel TigerLake-UP3 RVP (QDF# QXLC)&lt;/P&gt;
&lt;P&gt;Q: Please let us know the part number of the processor.&lt;BR /&gt;A: i7-1195G7&lt;/P&gt;
&lt;P&gt;Q: What is the name of the manufacturer, the part number, and where we can find the information if this request is related to a third-party design?&lt;BR /&gt;A: Intel RVP (QDF# QXLC)&lt;/P&gt;
&lt;P&gt;Q: Could you please let us know the Operating System (OS) related to this situation and its version?&lt;BR /&gt;A: Linux Ubuntu 20.04&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Thanks and Regards,&lt;/P&gt;
&lt;P&gt;&lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/272824"&gt;@Renuka18&lt;/a&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 27 Jan 2023 07:23:08 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Intel-Core-Processors/Coreboot-FSP-for-Tigerlake/m-p/1450658#M4417</guid>
      <dc:creator>Renuka18</dc:creator>
      <dc:date>2023-01-27T07:23:08Z</dc:date>
    </item>
    <item>
      <title>Re: Coreboot + FSP for Tigerlake</title>
      <link>https://community.intel.com/t5/Embedded-Intel-Core-Processors/Coreboot-FSP-for-Tigerlake/m-p/1450771#M4419</link>
      <description>&lt;P class="sub_section_element_selectors"&gt;Hello,&amp;nbsp;&lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/272824"&gt;@Renuka18&lt;/a&gt;:&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;Thanks for your clarification.&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;You need to update your profile to the premier option to help you. You should fill out the form stated on the following website:&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&lt;A class="sub_section_element_selectors" href="https://www.intel.com/content/www/us/en/forms/developer/premier-registration.html" target="_blank" rel="nofollow noopener noreferrer"&gt;https://www.intel.com/content/www/us/en/forms/developer/premier-registration.html&lt;/A&gt;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;You should use a business email address to evade any inconvenience. Please avoid the free email provider's address (such as the one provided by Hotmail, Gmail, Yahoo, or others).&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;Best regards,&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&lt;A class="sub_section_element_selectors" href="https://community.intel.com/t5/user/viewprofilepage/user-id/114" target="_blank" rel="noopener"&gt;@CarlosAM_INTEL&lt;/A&gt;.&lt;/P&gt;</description>
      <pubDate>Fri, 27 Jan 2023 16:40:03 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Intel-Core-Processors/Coreboot-FSP-for-Tigerlake/m-p/1450771#M4419</guid>
      <dc:creator>CarlosAM_INTEL</dc:creator>
      <dc:date>2023-01-27T16:40:03Z</dc:date>
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