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    <title>topic Re: intel IO margin tool issues on dual-RJ45 port. in Embedded Intel® Core™ Processors</title>
    <link>https://community.intel.com/t5/Embedded-Intel-Core-Processors/intel-IO-margin-tool-issues-on-dual-RJ45-port/m-p/1532848#M4792</link>
    <description>&lt;P&gt;&lt;SPAN&gt;Hello,&amp;nbsp;&lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/311609"&gt;@darren_wu&lt;/a&gt;:&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Thank you for contacting Intel Embedded Community.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;We received your request, but we want to address the following questions:&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Has the affected design been designed by a third-party developer or by you? &lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;In case it is a third-party device, what is the manufacturer's name and the device's part number?&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;In case it is your design, has the affected design been verified by Intel?&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;We are waiting for your answer.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Best regards,&lt;BR /&gt;&lt;A href="https://community.intel.com/t5/user/viewprofilepage/user-id/114?emcs_t=S2h8ZW1haWx8bWVudGlvbl9zdWJzY3JpcHRpb258TElXQ0JRMDhGQ1k2UFR8MTQ5NTk2MXxBVF9NRU5USU9OU3xoSw" target="_blank"&gt;@CarlosAM_INTEL&lt;/A&gt;.&lt;/SPAN&gt;&lt;/P&gt;</description>
    <pubDate>Wed, 11 Oct 2023 22:35:29 GMT</pubDate>
    <dc:creator>CarlosAM_INTEL</dc:creator>
    <dc:date>2023-10-11T22:35:29Z</dc:date>
    <item>
      <title>intel IO margin tool issues on dual-RJ45 port.</title>
      <link>https://community.intel.com/t5/Embedded-Intel-Core-Processors/intel-IO-margin-tool-issues-on-dual-RJ45-port/m-p/1532506#M4791</link>
      <description>&lt;P&gt;Hello There,&lt;BR /&gt;&lt;BR /&gt;I have an issue with using the IO margin tool to test our system, which will get a failed result.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;When I do test PCIE LAN port0can get pass result. Then, change to the PCIE LAN port1 and find the IOMT report fail result. (I had tried to find any error log, but I can't find anything.)&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;system config:&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;platform: x6211E&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;LAN IC: I210*2&lt;/STRONG&gt;&lt;/P&gt;</description>
      <pubDate>Wed, 11 Oct 2023 03:32:57 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Intel-Core-Processors/intel-IO-margin-tool-issues-on-dual-RJ45-port/m-p/1532506#M4791</guid>
      <dc:creator>darren_wu</dc:creator>
      <dc:date>2023-10-11T03:32:57Z</dc:date>
    </item>
    <item>
      <title>Re: intel IO margin tool issues on dual-RJ45 port.</title>
      <link>https://community.intel.com/t5/Embedded-Intel-Core-Processors/intel-IO-margin-tool-issues-on-dual-RJ45-port/m-p/1532848#M4792</link>
      <description>&lt;P&gt;&lt;SPAN&gt;Hello,&amp;nbsp;&lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/311609"&gt;@darren_wu&lt;/a&gt;:&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Thank you for contacting Intel Embedded Community.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;We received your request, but we want to address the following questions:&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Has the affected design been designed by a third-party developer or by you? &lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;In case it is a third-party device, what is the manufacturer's name and the device's part number?&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;In case it is your design, has the affected design been verified by Intel?&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;We are waiting for your answer.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Best regards,&lt;BR /&gt;&lt;A href="https://community.intel.com/t5/user/viewprofilepage/user-id/114?emcs_t=S2h8ZW1haWx8bWVudGlvbl9zdWJzY3JpcHRpb258TElXQ0JRMDhGQ1k2UFR8MTQ5NTk2MXxBVF9NRU5USU9OU3xoSw" target="_blank"&gt;@CarlosAM_INTEL&lt;/A&gt;.&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Wed, 11 Oct 2023 22:35:29 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Intel-Core-Processors/intel-IO-margin-tool-issues-on-dual-RJ45-port/m-p/1532848#M4792</guid>
      <dc:creator>CarlosAM_INTEL</dc:creator>
      <dc:date>2023-10-11T22:35:29Z</dc:date>
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