<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: Does the DDR Interface/Memory Controller of Tiger Lake UP3 i7-1186GRE Support ECC? in Embedded Intel® Core™ Processors</title>
    <link>https://community.intel.com/t5/Embedded-Intel-Core-Processors/Does-the-DDR-Interface-Memory-Controller-of-Tiger-Lake-UP3-i7/m-p/1654802#M5492</link>
    <description>&lt;P&gt;Hello,&amp;nbsp;&lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/404697"&gt;@lo3&lt;/a&gt;:&lt;/P&gt;
&lt;P&gt;Thank you for contacting Intel Embedded Community.&lt;/P&gt;
&lt;P&gt;The answer to your question is stated in the last row of the&amp;nbsp;Memory Specifications section of the following website:&lt;/P&gt;
&lt;P&gt;&lt;A href="https://www.intel.com/content/www/us/en/products/sku/208082/intel-core-i71185gre-processor-12m-cache-up-to-4-40-ghz/specifications.html" target="_blank"&gt;https://www.intel.com/content/www/us/en/products/sku/208082/intel-core-i71185gre-processor-12m-cache-up-to-4-40-ghz/specifications.html&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;Best regards,&lt;/P&gt;
&lt;P&gt;&lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/114"&gt;@CarlosAM_INTEL&lt;/a&gt;.&lt;/P&gt;</description>
    <pubDate>Mon, 06 Jan 2025 20:38:23 GMT</pubDate>
    <dc:creator>CarlosAM_INTEL</dc:creator>
    <dc:date>2025-01-06T20:38:23Z</dc:date>
    <item>
      <title>Does the DDR Interface/Memory Controller of Tiger Lake UP3 i7-1186GRE Support ECC?</title>
      <link>https://community.intel.com/t5/Embedded-Intel-Core-Processors/Does-the-DDR-Interface-Memory-Controller-of-Tiger-Lake-UP3-i7/m-p/1654507#M5488</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;I am conducting some research on the Intel Tiger Lake UP3 i7-1186GRE processor, specifically regarding its memory controller. I would like to know if the DDR interface/memory controller of this processor supports ECC (Error-Correcting Code) memory.&lt;/P&gt;&lt;P&gt;I haven’t been able to find any clear references to this in Intel's documentation or related technical materials. To avoid using incompatible memory, I would like to confirm whether this processor supports ECC memory. Additionally, if possible, I would appreciate any details on whether there are specific hardware or software requirements to enable ECC functionality.&lt;/P&gt;&lt;P&gt;Thank you for your help! Looking forward to your response!&lt;/P&gt;</description>
      <pubDate>Mon, 06 Jan 2025 03:09:17 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Intel-Core-Processors/Does-the-DDR-Interface-Memory-Controller-of-Tiger-Lake-UP3-i7/m-p/1654507#M5488</guid>
      <dc:creator>lo3</dc:creator>
      <dc:date>2025-01-06T03:09:17Z</dc:date>
    </item>
    <item>
      <title>Re: Does the DDR Interface/Memory Controller of Tiger Lake UP3 i7-1186GRE Support ECC?</title>
      <link>https://community.intel.com/t5/Embedded-Intel-Core-Processors/Does-the-DDR-Interface-Memory-Controller-of-Tiger-Lake-UP3-i7/m-p/1654802#M5492</link>
      <description>&lt;P&gt;Hello,&amp;nbsp;&lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/404697"&gt;@lo3&lt;/a&gt;:&lt;/P&gt;
&lt;P&gt;Thank you for contacting Intel Embedded Community.&lt;/P&gt;
&lt;P&gt;The answer to your question is stated in the last row of the&amp;nbsp;Memory Specifications section of the following website:&lt;/P&gt;
&lt;P&gt;&lt;A href="https://www.intel.com/content/www/us/en/products/sku/208082/intel-core-i71185gre-processor-12m-cache-up-to-4-40-ghz/specifications.html" target="_blank"&gt;https://www.intel.com/content/www/us/en/products/sku/208082/intel-core-i71185gre-processor-12m-cache-up-to-4-40-ghz/specifications.html&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;Best regards,&lt;/P&gt;
&lt;P&gt;&lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/114"&gt;@CarlosAM_INTEL&lt;/a&gt;.&lt;/P&gt;</description>
      <pubDate>Mon, 06 Jan 2025 20:38:23 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Intel-Core-Processors/Does-the-DDR-Interface-Memory-Controller-of-Tiger-Lake-UP3-i7/m-p/1654802#M5492</guid>
      <dc:creator>CarlosAM_INTEL</dc:creator>
      <dc:date>2025-01-06T20:38:23Z</dc:date>
    </item>
    <item>
      <title>Re: Does the DDR Interface/Memory Controller of Tiger Lake UP3 i7-1186GRE Support ECC?</title>
      <link>https://community.intel.com/t5/Embedded-Intel-Core-Processors/Does-the-DDR-Interface-Memory-Controller-of-Tiger-Lake-UP3-i7/m-p/1654918#M5493</link>
      <description>&lt;P&gt;Dear &lt;SPAN&gt;CarlosAM_INTEL&lt;/SPAN&gt;,&lt;/P&gt;&lt;P&gt;Thank you for your response.&lt;/P&gt;&lt;P&gt;I have reviewed the information on the website you provided and noted that the 1185GRE supports memory ECC. However, in document #575683 (as shown in the image below), it appears that ECC support is only available for the H-series. Could you kindly confirm again whether the UP3(i7-1186GRE) supports memory ECC?&lt;/P&gt;&lt;P&gt;Additionally, could you clarify what "N/A" means in the context of the LPDDR4x listed in the image below?&lt;/P&gt;&lt;P&gt;Looking forward to your confirmation.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="lo3_0-1736219886682.png" style="width: 400px;"&gt;&lt;img src="https://community.intel.com/t5/image/serverpage/image-id/61622iC6A584BA7D8A57D0/image-size/medium/is-moderation-mode/true?v=v2&amp;amp;px=400&amp;amp;whitelist-exif-data=Orientation%2CResolution%2COriginalDefaultFinalSize%2CCopyright" role="button" title="lo3_0-1736219886682.png" alt="lo3_0-1736219886682.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 07 Jan 2025 03:27:52 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Intel-Core-Processors/Does-the-DDR-Interface-Memory-Controller-of-Tiger-Lake-UP3-i7/m-p/1654918#M5493</guid>
      <dc:creator>lo3</dc:creator>
      <dc:date>2025-01-07T03:27:52Z</dc:date>
    </item>
    <item>
      <title>Re: Does the DDR Interface/Memory Controller of Tiger Lake UP3 i7-1186GRE Support ECC?</title>
      <link>https://community.intel.com/t5/Embedded-Intel-Core-Processors/Does-the-DDR-Interface-Memory-Controller-of-Tiger-Lake-UP3-i7/m-p/1655167#M5494</link>
      <description>&lt;P&gt;Hello,&amp;nbsp;&lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/404697"&gt;@lo3&lt;/a&gt;:&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Thanks for your reply.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;The information that may help you can be found in the document stated in the following website:&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp;&lt;A href="https://cdrdv2.intel.com/v1/dl/getContent/621597?explicitVersion=true" target="_blank"&gt;https://cdrdv2.intel.com/v1/dl/getContent/621597&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;In case you have problems with the provided website, you should request help by filling out the form stated on the following website:&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;&lt;A href="https://www.intel.com/content/www/us/en/forms/support/my-intel-sign-on-support.html" target="_blank" rel="noopener"&gt;https://www.intel.com/content/www/us/en/forms/support/my-intel-sign-on-support.html&lt;/A&gt; &amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Best regards,&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;&lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/114"&gt;@CarlosAM_INTEL&lt;/a&gt;.&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Tue, 07 Jan 2025 17:37:47 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Intel-Core-Processors/Does-the-DDR-Interface-Memory-Controller-of-Tiger-Lake-UP3-i7/m-p/1655167#M5494</guid>
      <dc:creator>CarlosAM_INTEL</dc:creator>
      <dc:date>2025-01-07T17:37:47Z</dc:date>
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  </channel>
</rss>

