<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: DDR4 Topology support Intel Xeon E-2276ME in Embedded Intel® Core™ Processors</title>
    <link>https://community.intel.com/t5/Embedded-Intel-Core-Processors/DDR4-Topology-support-Intel-Xeon-E-2276ME/m-p/1676691#M5576</link>
    <description>&lt;P class="sub_section_element_selectors"&gt;Hello&amp;nbsp;&lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/30636"&gt;@Pkaur&lt;/a&gt;,&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&lt;SPAN class="sub_section_element_selectors"&gt;Thank you for contacting Intel Embedded Community.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;Clamshell topology for memories are not supported, you can use Memory Down, UDIMM or SoDIMM. Please check section&amp;nbsp;#570805 - CFL EDS Vol1, section 2.&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;Processor's architecture is 64 bits. When ECC is used, it assigns some portion of the memory to it, you don't have to worry much about it.&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;You may check document #572062 - Design In, page 79, you have the Memory Configuration for ECC.&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;Best regards,&lt;BR /&gt;&lt;BR /&gt;&lt;A class="sub_section_element_selectors" href="https://community.intel.com/t5/user/viewprofilepage/user-id/266977" target="_blank" rel="noopener"&gt;@Diego_INTEL&lt;/A&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Fri, 21 Mar 2025 03:27:46 GMT</pubDate>
    <dc:creator>Diego_INTEL</dc:creator>
    <dc:date>2025-03-21T03:27:46Z</dc:date>
    <item>
      <title>DDR4 Topology support Intel Xeon E-2276ME</title>
      <link>https://community.intel.com/t5/Embedded-Intel-Core-Processors/DDR4-Topology-support-Intel-Xeon-E-2276ME/m-p/1674715#M5561</link>
      <description>&lt;P&gt;Hello Sir/Mam&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Does&amp;nbsp; Intel Xeon E-2276ME support 1R(single rank) clamshell topology? Can we map 2G X8 DDR4 in this topology?&amp;nbsp;&lt;/P&gt;&lt;P&gt;Another Query if we are using 32 Bits out of 64 Bits of DDR4 . Does ECC work in this case if yes where should it be mapped last 8 bit or in between?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 13 Mar 2025 09:41:09 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Intel-Core-Processors/DDR4-Topology-support-Intel-Xeon-E-2276ME/m-p/1674715#M5561</guid>
      <dc:creator>Pkaur</dc:creator>
      <dc:date>2025-03-13T09:41:09Z</dc:date>
    </item>
    <item>
      <title>Re: DDR4 Topology support Intel Xeon E-2276ME</title>
      <link>https://community.intel.com/t5/Embedded-Intel-Core-Processors/DDR4-Topology-support-Intel-Xeon-E-2276ME/m-p/1675376#M5569</link>
      <description>&lt;P&gt;Gentle reminder for the same&lt;/P&gt;</description>
      <pubDate>Mon, 17 Mar 2025 04:05:36 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Intel-Core-Processors/DDR4-Topology-support-Intel-Xeon-E-2276ME/m-p/1675376#M5569</guid>
      <dc:creator>Pkaur</dc:creator>
      <dc:date>2025-03-17T04:05:36Z</dc:date>
    </item>
    <item>
      <title>Re: DDR4 Topology support Intel Xeon E-2276ME</title>
      <link>https://community.intel.com/t5/Embedded-Intel-Core-Processors/DDR4-Topology-support-Intel-Xeon-E-2276ME/m-p/1676691#M5576</link>
      <description>&lt;P class="sub_section_element_selectors"&gt;Hello&amp;nbsp;&lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/30636"&gt;@Pkaur&lt;/a&gt;,&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&lt;SPAN class="sub_section_element_selectors"&gt;Thank you for contacting Intel Embedded Community.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;Clamshell topology for memories are not supported, you can use Memory Down, UDIMM or SoDIMM. Please check section&amp;nbsp;#570805 - CFL EDS Vol1, section 2.&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;Processor's architecture is 64 bits. When ECC is used, it assigns some portion of the memory to it, you don't have to worry much about it.&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;You may check document #572062 - Design In, page 79, you have the Memory Configuration for ECC.&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;Best regards,&lt;BR /&gt;&lt;BR /&gt;&lt;A class="sub_section_element_selectors" href="https://community.intel.com/t5/user/viewprofilepage/user-id/266977" target="_blank" rel="noopener"&gt;@Diego_INTEL&lt;/A&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 21 Mar 2025 03:27:46 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Intel-Core-Processors/DDR4-Topology-support-Intel-Xeon-E-2276ME/m-p/1676691#M5576</guid>
      <dc:creator>Diego_INTEL</dc:creator>
      <dc:date>2025-03-21T03:27:46Z</dc:date>
    </item>
  </channel>
</rss>

