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    <title>topic request a timing diagram and flow diagram for boot up/power up sequence for tiger lake up3 in Embedded Intel® Core™ Processors</title>
    <link>https://community.intel.com/t5/Embedded-Intel-Core-Processors/request-a-timing-diagram-and-flow-diagram-for-boot-up-power-up/m-p/1743538#M5954</link>
    <description>&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I will use the Intel Core i7-1186GRE Processor, tiger lake up3 (part number :FH8069004541901SRKXU) in my board. I would like to request a timing diagram and flow diagram for boot up/power up sequence? I will use the internal rail in PCH FIVR.&lt;/P&gt;&lt;P&gt;thanks,&lt;/P&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;</description>
    <pubDate>Tue, 07 Apr 2026 15:47:45 GMT</pubDate>
    <dc:creator>EsterLou</dc:creator>
    <dc:date>2026-04-07T15:47:45Z</dc:date>
    <item>
      <title>request a timing diagram and flow diagram for boot up/power up sequence for tiger lake up3</title>
      <link>https://community.intel.com/t5/Embedded-Intel-Core-Processors/request-a-timing-diagram-and-flow-diagram-for-boot-up-power-up/m-p/1743538#M5954</link>
      <description>&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I will use the Intel Core i7-1186GRE Processor, tiger lake up3 (part number :FH8069004541901SRKXU) in my board. I would like to request a timing diagram and flow diagram for boot up/power up sequence? I will use the internal rail in PCH FIVR.&lt;/P&gt;&lt;P&gt;thanks,&lt;/P&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;</description>
      <pubDate>Tue, 07 Apr 2026 15:47:45 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Intel-Core-Processors/request-a-timing-diagram-and-flow-diagram-for-boot-up-power-up/m-p/1743538#M5954</guid>
      <dc:creator>EsterLou</dc:creator>
      <dc:date>2026-04-07T15:47:45Z</dc:date>
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    <item>
      <title>Re:request a timing diagram and flow diagram for boot up/power up sequence for tiger lake up3</title>
      <link>https://community.intel.com/t5/Embedded-Intel-Core-Processors/request-a-timing-diagram-and-flow-diagram-for-boot-up-power-up/m-p/1743554#M5955</link>
      <description>&lt;P&gt;Hi &lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/477724"&gt;@EsterLou&lt;/a&gt;,&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Thank you for reaching out. To ensure you receive the most accurate and timely assistance, I'm redirecting your inquiry to our specialized forum that focuses specifically on these types of issues. The experts there will be better equipped to help you quickly.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Best regards, &lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Archie D. &lt;/P&gt;&lt;P&gt;Intel Customer Support Engineer&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Tue, 07 Apr 2026 18:01:59 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Intel-Core-Processors/request-a-timing-diagram-and-flow-diagram-for-boot-up-power-up/m-p/1743554#M5955</guid>
      <dc:creator>ArchieD_Intel</dc:creator>
      <dc:date>2026-04-07T18:01:59Z</dc:date>
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