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    <title>topic A question about memory controller in Embedded Intel® Core™ Processors</title>
    <link>https://community.intel.com/t5/Embedded-Intel-Core-Processors/A-question-about-memory-controller/m-p/199521#M598</link>
    <description>&lt;P&gt;Dear sir&lt;/P&gt;&lt;P&gt;     Recently I get a confusion about memory controller.I measured the signal of DDR CMD signal like CAS,RAS based on skylake &lt;A href="http://platform.It"&gt;platform.It&lt;/A&gt; show the oscillogram below.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;It seems that the CAS signal has a tristate.But the CMD signal is pull up to VTT(0.6v) on our board.I suspect that the low level and the high level are drived by memory &lt;A href="http://controller.So"&gt;controller.So&lt;/A&gt; I hope I can confirm my idea here.Thanks!&lt;/P&gt;</description>
    <pubDate>Thu, 07 Jan 2016 10:47:40 GMT</pubDate>
    <dc:creator>idata</dc:creator>
    <dc:date>2016-01-07T10:47:40Z</dc:date>
    <item>
      <title>A question about memory controller</title>
      <link>https://community.intel.com/t5/Embedded-Intel-Core-Processors/A-question-about-memory-controller/m-p/199521#M598</link>
      <description>&lt;P&gt;Dear sir&lt;/P&gt;&lt;P&gt;     Recently I get a confusion about memory controller.I measured the signal of DDR CMD signal like CAS,RAS based on skylake &lt;A href="http://platform.It"&gt;platform.It&lt;/A&gt; show the oscillogram below.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;It seems that the CAS signal has a tristate.But the CMD signal is pull up to VTT(0.6v) on our board.I suspect that the low level and the high level are drived by memory &lt;A href="http://controller.So"&gt;controller.So&lt;/A&gt; I hope I can confirm my idea here.Thanks!&lt;/P&gt;</description>
      <pubDate>Thu, 07 Jan 2016 10:47:40 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Intel-Core-Processors/A-question-about-memory-controller/m-p/199521#M598</guid>
      <dc:creator>idata</dc:creator>
      <dc:date>2016-01-07T10:47:40Z</dc:date>
    </item>
    <item>
      <title>Re: A question about memory controller</title>
      <link>https://community.intel.com/t5/Embedded-Intel-Core-Processors/A-question-about-memory-controller/m-p/199522#M599</link>
      <description>&lt;P&gt;Hello Fupeng_Wang,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you for contacting the Intel Embedded Community.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We will contact you via email in order to help you.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Carlos_A.&lt;/P&gt;</description>
      <pubDate>Thu, 07 Jan 2016 15:06:59 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Intel-Core-Processors/A-question-about-memory-controller/m-p/199522#M599</guid>
      <dc:creator>CarlosAM_INTEL</dc:creator>
      <dc:date>2016-01-07T15:06:59Z</dc:date>
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