<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: Queries Regarding XL710-BM1 in Embedded Connectivity</title>
    <link>https://community.intel.com/t5/Embedded-Connectivity/Queries-Regarding-XL710-BM1/m-p/1464129#M4349</link>
    <description>&lt;P&gt;Hi &lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/266977"&gt;@Diego_INTEL&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Thanks for your response.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;We have below understanding based on "section&amp;nbsp;&lt;SPAN&gt;3.2.6 Possible port to physical lane configurations for various PHY interfaces”.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;For Quad Port SFP+ application, we can use Serdes lane combination provided for Cfg. ID 7.0, 7.1 and 7.2 given into table 3-78.&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Aditya_Singh_0-1678439918650.png" style="width: 400px;"&gt;&lt;img src="https://community.intel.com/t5/image/serverpage/image-id/38901i43A4099153EC4A10/image-size/medium/is-moderation-mode/true?v=v2&amp;amp;px=400&amp;amp;whitelist-exif-data=Orientation%2CResolution%2COriginalDefaultFinalSize%2CCopyright" role="button" title="Aditya_Singh_0-1678439918650.png" alt="Aditya_Singh_0-1678439918650.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;All the Serdes lanes will be available into XL710-BM1 variant. Also, only one MAC port will be available into XL710-BM1 variant.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Please let us know otherwise.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Regards,&lt;/P&gt;
&lt;P&gt;Aditya&lt;/P&gt;</description>
    <pubDate>Fri, 10 Mar 2023 09:22:52 GMT</pubDate>
    <dc:creator>Aditya_Singh</dc:creator>
    <dc:date>2023-03-10T09:22:52Z</dc:date>
    <item>
      <title>Queries Regarding XL710-BM1</title>
      <link>https://community.intel.com/t5/Embedded-Connectivity/Queries-Regarding-XL710-BM1/m-p/1463627#M4342</link>
      <description>&lt;P&gt;Hi Intel Team,&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Posting our queries here as per suggestion from&amp;nbsp;&lt;SPAN&gt;Ethernet Products support team. Below is the link for the case-&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;&lt;A href="https://community.intel.com/t5/Ethernet-Products/Queries-Regarding-XL710-BM1/m-p/1460547#M32393" target="_self"&gt;Queries Regarding XL710-BM1&lt;/A&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&lt;SPAN class="sub_section_element_selectors"&gt;While browsing through datasheet of&lt;/SPAN&gt;&lt;SPAN class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;A class="sub_section_element_selectors" href="https://ark.intel.com/content/www/us/en/ark/products/93104/intel-ethernet-controller-xl710bm1.html" target="_self" rel="nofollow noopener noreferrer"&gt;&lt;SPAN class="sub_section_element_selectors"&gt;XL710&lt;/SPAN&gt;&lt;/A&gt;&lt;SPAN class="sub_section_element_selectors"&gt;, I found that there is only one package given in section 13.7-&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Aditya_Singh_0-1678347394012.png" style="width: 400px;"&gt;&lt;img src="https://community.intel.com/t5/image/serverpage/image-id/38841i04D5381B4BCF3E39/image-size/medium/is-moderation-mode/true?v=v2&amp;amp;px=400&amp;amp;whitelist-exif-data=Orientation%2CResolution%2COriginalDefaultFinalSize%2CCopyright" role="button" title="Aditya_Singh_0-1678347394012.png" alt="Aditya_Singh_0-1678347394012.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&lt;SPAN class="sub_section_element_selectors"&gt;There are total 8 Serdes lanes are available in XL710 series divided into two groups Group A and Group B. Please refer to table 2-3 into the datasheet.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Aditya_Singh_1-1678347394162.png" style="width: 400px;"&gt;&lt;img src="https://community.intel.com/t5/image/serverpage/image-id/38842i71854BC84CFC5A93/image-size/medium/is-moderation-mode/true?v=v2&amp;amp;px=400&amp;amp;whitelist-exif-data=Orientation%2CResolution%2COriginalDefaultFinalSize%2CCopyright" role="button" title="Aditya_Singh_1-1678347394162.png" alt="Aditya_Singh_1-1678347394162.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&lt;SPAN class="sub_section_element_selectors"&gt;As per product brief of XL710-BM1, it can support 4 x10GbE SFI modules.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&lt;SPAN class="sub_section_element_selectors"&gt;Below are our queries-&lt;/SPAN&gt;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&lt;SPAN class="sub_section_element_selectors"&gt;1) Which group (group A or group B) will be available into XL710-BM1 variant&lt;/SPAN&gt;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&lt;SPAN class="sub_section_element_selectors"&gt;2) Is there any difference between package of XL710-BM1 and&amp;nbsp; XL710-BM2 variant&lt;/SPAN&gt;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&lt;SPAN class="sub_section_element_selectors"&gt;3) Section 1.1 shows the block diagram for XL710 series-&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Aditya_Singh_2-1678347394066.png" style="width: 400px;"&gt;&lt;img src="https://community.intel.com/t5/image/serverpage/image-id/38843iEA4427FA8E6DCDB1/image-size/medium/is-moderation-mode/true?v=v2&amp;amp;px=400&amp;amp;whitelist-exif-data=Orientation%2CResolution%2COriginalDefaultFinalSize%2CCopyright" role="button" title="Aditya_Singh_2-1678347394066.png" alt="Aditya_Singh_2-1678347394066.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&lt;SPAN class="sub_section_element_selectors"&gt;There are two block diagrams showing below information&lt;/SPAN&gt;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&lt;SPAN class="sub_section_element_selectors"&gt;a) As per figure 1-5 XL710 series supports: 2x 40G or 4x 10G/1G&lt;/SPAN&gt;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&lt;SPAN class="sub_section_element_selectors"&gt;b) As per figure 1-7 XL710 series supports: 2x40G or 4x 10G/1G/100M&lt;/SPAN&gt;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&lt;SPAN class="sub_section_element_selectors"&gt;Which XL710 variant supports option "A" and option "B"&lt;/SPAN&gt;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&lt;SPAN class="sub_section_element_selectors"&gt;Regards,&lt;/SPAN&gt;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&lt;SPAN class="sub_section_element_selectors"&gt;Aditya&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Thu, 09 Mar 2023 07:38:09 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Connectivity/Queries-Regarding-XL710-BM1/m-p/1463627#M4342</guid>
      <dc:creator>Aditya_Singh</dc:creator>
      <dc:date>2023-03-09T07:38:09Z</dc:date>
    </item>
    <item>
      <title>Re: Queries Regarding XL710-BM1</title>
      <link>https://community.intel.com/t5/Embedded-Connectivity/Queries-Regarding-XL710-BM1/m-p/1463856#M4347</link>
      <description>&lt;P&gt;Hello &lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/275814"&gt;@Aditya_Singh&lt;/a&gt;:&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Thank you for contacting Intel Embedded Community.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;The Package Size is 25 x 25 mm, the difference in both SKUs is the port number.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;You can check the section of the datasheet “3.2.6 Possible port to physical lane configurations for various PHY interfaces”, as for example this function is only for the BM2: “Dual 40 GbE — XL710-AM2 and XL710-BM2 SKUs are supported”&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;The figures, yes, they are confusing, both SKUs should support the 100M too, because the registry is the same for both, as you can see in the section “10.2.2.3 MAC Registers”, but in the end, the connections of the section 3.2.6 and the port numbers (single or dual) of each SKU is what you can check for your design.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Best regards,&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/266977"&gt;@Diego_INTEL&lt;/a&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 09 Mar 2023 20:04:01 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Connectivity/Queries-Regarding-XL710-BM1/m-p/1463856#M4347</guid>
      <dc:creator>Diego_INTEL</dc:creator>
      <dc:date>2023-03-09T20:04:01Z</dc:date>
    </item>
    <item>
      <title>Re: Queries Regarding XL710-BM1</title>
      <link>https://community.intel.com/t5/Embedded-Connectivity/Queries-Regarding-XL710-BM1/m-p/1464129#M4349</link>
      <description>&lt;P&gt;Hi &lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/266977"&gt;@Diego_INTEL&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Thanks for your response.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;We have below understanding based on "section&amp;nbsp;&lt;SPAN&gt;3.2.6 Possible port to physical lane configurations for various PHY interfaces”.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;For Quad Port SFP+ application, we can use Serdes lane combination provided for Cfg. ID 7.0, 7.1 and 7.2 given into table 3-78.&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Aditya_Singh_0-1678439918650.png" style="width: 400px;"&gt;&lt;img src="https://community.intel.com/t5/image/serverpage/image-id/38901i43A4099153EC4A10/image-size/medium/is-moderation-mode/true?v=v2&amp;amp;px=400&amp;amp;whitelist-exif-data=Orientation%2CResolution%2COriginalDefaultFinalSize%2CCopyright" role="button" title="Aditya_Singh_0-1678439918650.png" alt="Aditya_Singh_0-1678439918650.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;All the Serdes lanes will be available into XL710-BM1 variant. Also, only one MAC port will be available into XL710-BM1 variant.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Please let us know otherwise.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Regards,&lt;/P&gt;
&lt;P&gt;Aditya&lt;/P&gt;</description>
      <pubDate>Fri, 10 Mar 2023 09:22:52 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Connectivity/Queries-Regarding-XL710-BM1/m-p/1464129#M4349</guid>
      <dc:creator>Aditya_Singh</dc:creator>
      <dc:date>2023-03-10T09:22:52Z</dc:date>
    </item>
    <item>
      <title>Re: Queries Regarding XL710-BM1</title>
      <link>https://community.intel.com/t5/Embedded-Connectivity/Queries-Regarding-XL710-BM1/m-p/1464391#M4355</link>
      <description>&lt;P&gt;Hello&amp;nbsp;&lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/275814"&gt;@Aditya_Singh&lt;/a&gt;:&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Yes, that should work.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;In section 3.2.2&amp;nbsp; &lt;SPAN class="fontstyle0"&gt;Physical Layer (PHY)&lt;/SPAN&gt;&amp;nbsp;says "&lt;SPAN class="fontstyle0"&gt;X710/XXV710/XL710 supports eight physical high speed SerDes lanes, each capable of operating at up to 10.3125 GBaud.&lt;/SPAN&gt;"&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;Best regards,&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&lt;A class="sub_section_element_selectors" href="https://community.intel.com/t5/user/viewprofilepage/user-id/266977" target="_blank"&gt;@Diego_INTEL&lt;/A&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 10 Mar 2023 20:43:03 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Connectivity/Queries-Regarding-XL710-BM1/m-p/1464391#M4355</guid>
      <dc:creator>Diego_INTEL</dc:creator>
      <dc:date>2023-03-10T20:43:03Z</dc:date>
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  </channel>
</rss>

