topic Re: Problems with I210 and external PHYs in Embedded Connectivity

Problems with I210 and external PHYs

PWilc1 — Thu, 18 Feb 2016 01:57:08 GMT

Dear All,

We have a board with two I210 parts on it.

The I210 communicates with a PHY on a daughter card.

We have two different types of daughter card. One has

a Marvell 88E1111 device and the other has a Marvell 88E1512

part on it.

I turned on the debugging messages in the Intel driver software.

With the 88E1512 board, I see a lot of routines being called,

but the PHY doesn't get set up correctly. On power up the

RJ45 side of the PHY gets linkup to a switch, but not after

the driver code runs. So, my question is has this particular

combination of I210 and PHY been tested recently? It

obviously requires a lot of work to test every release of

software with every possible hardware permutation.

With the 88E1111 we have problems with getting occasional MDIO errors

when the I210 is doing MDIO reads. On reading the code, the

"MDI Error" message is triggered by the MDI_ERR bit being

set in the I210's MDIC register (0x20).

On page 377 of the I210 manual, there is the statement:

This bit is set to 1b by hardware when it fails to complete an MDI read.

Software should make sure this bit is clear (0b) before issuing an MDI read

or write command.

My question is what triggers the setting of this bit? The MDIO

protocol has no handshaking with the MDIO slave. If there is

no slave at all, the MDIO master will just drive the read pattern,

followed by the PHY address and register address. After that the

pull-up will pull the MDIO data line high, and all ones will be read.

How do you get an error?

Thanks, Paul.

Re: Problems with I210 and external PHYs

CarlosAM_INTEL — Thu, 18 Feb 2016 19:47:25 GMT

Hello PVWB,

Thank you for contacting the Intel Embedded Community.

We suggest you to follow the suggestions provided to you in the Forum Carlos_A.

Re: Problems with I210 and external PHYs

PWilc1 — Thu, 18 Feb 2016 21:59:56 GMT

I think I have figured this out. It declares an error if it

ever reads all ones, as happens when the MDIO target is

missing. I assume you get this error if you read a register

that really is all ones!

However, now I have the MDIO transfers working to

the 88E1111, I find I get a similar behaviour to that

I had with the 88E1512 parts. After the code runs,

the RJ45 link between PHY and the external switch

goes down. At power up, the link comes up. Is it

possible that there is a problem with the code that

sets up these PHYs. I realize that not many people

use the I210 with an external RJ45 PHY.

Thanks, Paul.

Re: Problems with I210 and external PHYs

CarlosAM_INTEL — Fri, 19 Feb 2016 13:38:23 GMT

Hello PVWB,

Thanks for your reply.

In order to better understand this situation, we would like to address the following questions:

Could you please tell us the Operating System (OS), driver version, NVM image use to talk to these external PHY?

Could you please inform us know how long are the traces to the PHY?

Could you please let us know the type of connection is being used?

Could you please confirm if this design has been looked by Intel?

These questions have been addressed to have more information of the design and usage model, in order to have a better idea of the problem and give you the proper information.

It is important to let you know that the 88E1111 is supported with our drivers, we have idea that the 88E1512 is unsupported. In case that you want to work with an unsupported device, you should build your own driver.

Thanks again for your collaboration.

Best Regards,

Carlos_A.

Re: Problems with I210 and external PHYs

PWilc1 — Tue, 23 Feb 2016 00:39:52 GMT

Dear Carlos,

The two I210 devices starting working on Friday.

Here is a summary of what we had to do:

We changed the Initialization control word 3 (0x24) from 0x4220

to 0x4224. This turns on the external MDIO mode. My guess

is the original used I2C with an SFP. We also had to update

the checksum.

The correct PHY address has to be specified in Flash word 0x13

(Initialization control word 4). This is probably relevant to

the other person having trouble with SGMII operation with an

SFP. (P 187 of the I210 manual)

There is a bug somewhere in the code that powers down the

PHY. This is the 0x800 bit in PHY word 0, for at least the

88E1111. We did the rude hack of adding the following to the

e1000_write_phy_reg_mdic routine:

if (offset == 0 && (data & 0x800)) data ^= 0x800; // Rude hack

This solves the power down problem, if not very elegantly!

There is another, probably mostly harmless bug around line 275

and 334 of e1000_phy.c. This puts the PHY address in the register E1000_MDIC,

(0x20) (p 376), reserved area. For the I210, the PHY address

is stored in I210 register E1000_MDICNFG, (0xE04) (p 377).

The other effect of this is, if code elsewhere changes the value of

phy->addr, these changes will not get copied into E1000_MDICNFG,

so the address loaded from the Flash will continue to be used

for the MDIO transfers.

Our starting image was

Flash_images/I210/SGMII/Dev_Start_I210_Sgmii_NOMNG_16Mb_A2_3.25_0.03.bin

Re: Problems with I210 and external PHYs

CarlosAM_INTEL — Tue, 23 Feb 2016 15:47:28 GMT

Hello PVWB,

Thanks for share the way that you solve your problem.

We are glad to hear that your problem has been solved.

Please do not hesitate to contact us again if you have more questions related to Intel Embedded products.

Best Regards,

Carlos_A.