<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: Questions about Thunderbolt 4 controller specifications and performance. in Embedded Connectivity</title>
    <link>https://community.intel.com/t5/Embedded-Connectivity/Questions-about-Thunderbolt-4-controller-specifications-and/m-p/1547043#M4902</link>
    <description>&lt;P&gt;Diego,&lt;/P&gt;&lt;P&gt;Thank you for the explanation.&lt;/P&gt;&lt;P&gt;But why would Intel reduce the number of PCIe 3.0 lanes, in the peripheral (device) controller from a x4 PCIe End-point (JHL7440) with TB3 to a x1&amp;nbsp;PCIe End-point (JHL8440) with TB4?&lt;/P&gt;&lt;P&gt;Thanks again for your time.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Fri, 24 Nov 2023 08:11:27 GMT</pubDate>
    <dc:creator>fp5849</dc:creator>
    <dc:date>2023-11-24T08:11:27Z</dc:date>
    <item>
      <title>Questions about Thunderbolt 4 controller specifications and performance.</title>
      <link>https://community.intel.com/t5/Embedded-Connectivity/Questions-about-Thunderbolt-4-controller-specifications-and/m-p/1545306#M4891</link>
      <description>&lt;P&gt;I have been told that the reason a peripheral Thunderbolt 4 drive enclosure (PCIe NVMe M.2 2280 M Key) provides a link speed test result of only 770MB/s to a Thunderbolt 4 Host, is because the Thunderbolt 4 controllers only supports one (1) PCIe 3.0 lane (PCIe 3.0 x1), as compared to the two (2) or four (4) PCIe 3.0 lanes supported by Thunderbolt 3 controllers.&lt;/P&gt;&lt;P&gt;Is this correct?&lt;/P&gt;&lt;P&gt;The vendor for the Thunderbolt 4 drive enclosure (PCIe NVMe M.2) also stated that the&amp;nbsp;link speed test results, to a Thunderbolt 3 Host, for their other equivalent Thunderbolt 3 drive enclosures, have&amp;nbsp;not been an issue because Thunderbolt 3 supports PCIe 3.0 x2, x4 lanes for Thunderbolt 3 M.2 &amp;nbsp;2280 NVMe peripheral devices.&lt;/P&gt;&lt;P&gt;The vendor will not disclose whose Thunderbolt 4 Controller chip-set they are using.&lt;/P&gt;&lt;P&gt;But referencing the&amp;nbsp;&lt;SPAN&gt;&lt;STRONG&gt;Intel&lt;/STRONG&gt; &lt;STRONG&gt;JHL8440&lt;/STRONG&gt; Thunderbolt 4 (peripheral)&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;Controller Product Specifications, at:&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;A href="https://ark.intel.com/content/www/us/en/ark/products/189982/intel-jhl8440-thunderbolt-4-controller.html" target="_blank" rel="noopener"&gt;https://ark.intel.com/content/www/us/en/ark/products/189982/intel-jhl8440-thunderbolt-4-controller.html&lt;/A&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;I find the following:&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;STRONG&gt;Supplemental Information&lt;/STRONG&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;UL class=""&gt;&lt;LI&gt;&lt;SPAN class=""&gt;Description:&lt;/SPAN&gt; &lt;SPAN class=""&gt;+ Thunderbolt™/USB4 peripheral support at 40G&lt;BR /&gt;+ Native USB Type-C interface capabilities: USB2, USB3 (10G), DP1.4 Alt-mode&lt;BR /&gt;+ Tunneling capabilities (32G PCIe, USB3(10G), 2 displays (up to DP1.4)&lt;BR /&gt;+ Other native interfaces: x1 PCIe 8GT/s, 1x USB3 (10G)&lt;/SPAN&gt;&lt;/LI&gt;&lt;/UL&gt;&lt;/DIV&gt;&lt;P&gt;&lt;SPAN&gt;&lt;STRONG&gt;I/O Specifications&lt;/STRONG&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;&lt;SPAN class=""&gt;Port Configuration:&lt;/SPAN&gt; &lt;SPAN class=""&gt;Quad&lt;/SPAN&gt;&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;This description for the &lt;STRONG&gt;Intel&lt;/STRONG&gt; &lt;STRONG&gt;JHL8440&lt;/STRONG&gt; states:&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;1)&amp;nbsp;Tunneling capabilities (32G PCIe ...&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;and&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;2)&amp;nbsp;Other native interfaces: x1 PCIe 8GT/s...&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Does&amp;nbsp;&amp;nbsp;"x1 PCIe 8GT/s" mean that this Thunderbolt 4 controller only supports one (1) PCIe 3.0 lane in the "link" to the Thunderbolt 4 Host controller?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;Would this be why the&amp;nbsp;Thunderbolt 4 drive enclosure (PCIe NVMe M.2) is only providing a link speed test result of 770MB/s to the Thunderbolt 4 Host?&lt;/P&gt;&lt;P&gt;If not, will someone please explain what is meant by the reference "x1 PCIe 8GT/s" reference?&lt;/P&gt;&lt;P&gt;It is my understanding that 8GT/s is the raw data transfer speed, in this case of 8Gb/s. Correct?&lt;/P&gt;&lt;P&gt;And the&amp;nbsp;"32G PCIe" refers to the minimum data transfer requirement of Thunderbolt 4. Correct?&lt;/P&gt;&lt;P&gt;Also, would someone offer an opinion as to why a Thunderbolt 4 peripheral would have a 770 MB/s link speed test result?&lt;/P&gt;&lt;P&gt;In addition, I believe that the Thunderbolt 4 (Host) controller would be the &lt;SPAN&gt;&lt;STRONG&gt;Intel&lt;/STRONG&gt;&lt;/SPAN&gt;&amp;nbsp;&lt;STRONG&gt;JHL8540&lt;/STRONG&gt;&amp;nbsp;or the&amp;nbsp;&lt;SPAN&gt;&lt;STRONG&gt;Intel&amp;nbsp;&lt;/STRONG&gt;&lt;/SPAN&gt;&lt;STRONG&gt;JHL8340&lt;/STRONG&gt; controller.&lt;/P&gt;&lt;P&gt;If this is correct, should the&amp;nbsp;&lt;STRONG&gt;Intel&lt;/STRONG&gt;&amp;nbsp;&lt;STRONG&gt;JHL8540&lt;/STRONG&gt;&amp;nbsp;and the&amp;nbsp;&lt;SPAN&gt;&lt;STRONG&gt;Intel&amp;nbsp;&lt;/STRONG&gt;&lt;/SPAN&gt;&lt;STRONG&gt;JHL8340&lt;/STRONG&gt; controllers have the same specifications, as published for the&amp;nbsp;&lt;STRONG&gt;Intel&lt;/STRONG&gt; &lt;STRONG&gt;JHL8440&lt;/STRONG&gt;?&lt;/P&gt;&lt;P&gt;I ask this because the information provided by the&amp;nbsp;&lt;STRONG&gt;Intel&lt;/STRONG&gt;&amp;nbsp;&lt;STRONG&gt;JHL8540&lt;/STRONG&gt;&amp;nbsp;and&amp;nbsp;&lt;SPAN&gt;&lt;STRONG&gt;Intel&amp;nbsp;&lt;/STRONG&gt;&lt;/SPAN&gt;&lt;STRONG&gt;JHL8340&amp;nbsp;&lt;/STRONG&gt;Thunderbolt 4&amp;nbsp;Controller Product Specifications, at the following links&amp;nbsp;are not the same as the&amp;nbsp;&lt;STRONG&gt;Intel&lt;/STRONG&gt; &lt;STRONG&gt;JHL8440.&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;A href="https://ark.intel.com/content/www/us/en/ark/products/193684/intel-jhl8540-thunderbolt-4-controller.html" target="_blank" rel="noopener"&gt;https://ark.intel.com/content/www/us/en/ark/products/193684/intel-jhl8540-thunderbolt-4-controller.html&lt;/A&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;and&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;A href="https://ark.intel.com/content/www/us/en/ark/products/193688/intel-jhl8340-thunderbolt-4-controller.html" target="_blank" rel="noopener"&gt;https://ark.intel.com/content/www/us/en/ark/products/193688/intel-jhl8340-thunderbolt-4-controller.html&lt;/A&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Here is what is provided by the&amp;nbsp;&lt;STRONG&gt;Intel&lt;/STRONG&gt;&amp;nbsp;&lt;STRONG&gt;JHL8540&lt;/STRONG&gt;&amp;nbsp;and&amp;nbsp;&lt;STRONG&gt;Intel&amp;nbsp;&lt;/STRONG&gt;&lt;STRONG&gt;JHL8340&amp;nbsp;&lt;/STRONG&gt;Thunderbolt 4&amp;nbsp;Controller Product Specifications.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;STRONG&gt;I/O Specifications&lt;/STRONG&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;&lt;SPAN class=""&gt;&lt;A target="_blank"&gt;&lt;SPAN&gt;PCI Express Configurations ‡&lt;/SPAN&gt;&lt;/A&gt; &lt;/SPAN&gt;&lt;SPAN class=""&gt;x4 Gen3&lt;BR /&gt;capabilities: ACS, FPB, PTM, P2P, 128b payload&lt;BR /&gt;&lt;/SPAN&gt;&lt;/LI&gt;&lt;LI&gt;&lt;SPAN class=""&gt;Display Port&lt;/SPAN&gt; &lt;SPAN class=""&gt;2 DP Sink, 1 DP SRC, DP1.4a tunnel/re-drive&lt;BR /&gt;x1/x2/x4 1.62/2.7/5.4/8.1&lt;/SPAN&gt;&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;&amp;nbsp;Thank you, in advance, for your time and assistance with addressing my questions.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;</description>
      <pubDate>Sun, 19 Nov 2023 09:15:24 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Connectivity/Questions-about-Thunderbolt-4-controller-specifications-and/m-p/1545306#M4891</guid>
      <dc:creator>fp5849</dc:creator>
      <dc:date>2023-11-19T09:15:24Z</dc:date>
    </item>
    <item>
      <title>Re: Questions about Thunderbolt 4 controller specifications and performance.</title>
      <link>https://community.intel.com/t5/Embedded-Connectivity/Questions-about-Thunderbolt-4-controller-specifications-and/m-p/1546717#M4897</link>
      <description>&lt;P class="sub_section_element_selectors"&gt;Hello&amp;nbsp;&lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/324520"&gt;@fp5849&lt;/a&gt;,&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;Thank you for contacting Intel Embedded Community.&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&lt;SPAN&gt;"Thunderbolt 4 drive enclosure (PCIe NVMe M.2 2280 M Key) provides a link speed test result of only 770MB/s to a Thunderbolt 4 Host, is because the Thunderbolt 4 controllers only supports one (1) PCIe 3.0 lane (PCIe 3.0 x1), as compared to the two (2) or four (4) PCIe 3.0 lanes supported by Thunderbolt 3 controllers."&lt;/SPAN&gt;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;Seems correct, we have that with 1 lane, it can be transferred up to 985 MB/s at 8 GT/s, I find that the speed is accurate, because:&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;Version 3.x: 8 GT/s&lt;BR /&gt;x1: 985 MB/s&lt;BR /&gt;x16: 15.75 GB/s&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&lt;A href="https://en.wikipedia.org/wiki/PCI_Express" target="_blank"&gt;https://en.wikipedia.org/wiki/PCI_Express&lt;/A&gt;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&lt;A href="https://paolozaino.wordpress.com/2013/05/21/converting-gts-to-gbps/" target="_blank"&gt;https://paolozaino.wordpress.com/2013/05/21/converting-gts-to-gbps/&lt;/A&gt;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;So, in this case, let's do some conversions:&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;8 GT/s x (128b/130b) = 7.877 Gbps -&amp;gt; Converting bit to byte -&amp;gt; 7.877/8 GB/s = 984.62 MB/s&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;As for the test result being 770 MB/s I'm not sure, it seems there is something else to take into account, but the result seems realistic with 1 lane.&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;Now, the controller has 4 lanes more that can be tunneled through the&amp;nbsp;Thunderbolt/USB4, and use a 4 lane PCIe, that is the 32 GT/s that is mentioned too, but as a PCIe Phy, it only has one lane, the other lines must be used through the USB4.&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;I think that the devices that can be compared together are these, as they are an Accessory Controller,&amp;nbsp;that act as a Hub or a point of exit in the Thunderbolt/USB4 domain:&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;Goshen Ridge - JHL8440 -&amp;gt; x1 PCIe Gen 3&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&lt;SPAN class="fontstyle0"&gt;Titan Ridge - JHL7440 -&amp;gt; 4x PCIe Gen 3&lt;/SPAN&gt;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;The Maple Ridge controllers, the Intel JHL8540 and the Intel JHL8340, are Host Controllers,&amp;nbsp;that act as a point of entry in the Thunderbolt/USB4 domain.&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;Also, you may use the Thunderbolt support if you need further help:&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&lt;A href="https://www.thunderbolttechnology.net/contact" target="_blank"&gt;https://www.thunderbolttechnology.net/contact&lt;/A&gt;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;Best regards,&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&lt;A class="sub_section_element_selectors" href="https://community.intel.com/t5/user/viewprofilepage/user-id/266977?emcs_t=S2h8ZW1haWx8dG9waWNfc3Vic2NyaXB0aW9ufExMNDhLVVI2SDhQSlZTfDE1MTI2NTh8U1VCU0NSSVBUSU9OU3xoSw" target="_blank" rel="noopener"&gt;@Diego_INTEL&lt;/A&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 23 Nov 2023 04:55:44 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Connectivity/Questions-about-Thunderbolt-4-controller-specifications-and/m-p/1546717#M4897</guid>
      <dc:creator>Diego_INTEL</dc:creator>
      <dc:date>2023-11-23T04:55:44Z</dc:date>
    </item>
    <item>
      <title>Re: Questions about Thunderbolt 4 controller specifications and performance.</title>
      <link>https://community.intel.com/t5/Embedded-Connectivity/Questions-about-Thunderbolt-4-controller-specifications-and/m-p/1547043#M4902</link>
      <description>&lt;P&gt;Diego,&lt;/P&gt;&lt;P&gt;Thank you for the explanation.&lt;/P&gt;&lt;P&gt;But why would Intel reduce the number of PCIe 3.0 lanes, in the peripheral (device) controller from a x4 PCIe End-point (JHL7440) with TB3 to a x1&amp;nbsp;PCIe End-point (JHL8440) with TB4?&lt;/P&gt;&lt;P&gt;Thanks again for your time.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 24 Nov 2023 08:11:27 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Connectivity/Questions-about-Thunderbolt-4-controller-specifications-and/m-p/1547043#M4902</guid>
      <dc:creator>fp5849</dc:creator>
      <dc:date>2023-11-24T08:11:27Z</dc:date>
    </item>
    <item>
      <title>Re: Questions about Thunderbolt 4 controller specifications and performance.</title>
      <link>https://community.intel.com/t5/Embedded-Connectivity/Questions-about-Thunderbolt-4-controller-specifications-and/m-p/1547326#M4903</link>
      <description>&lt;P class="sub_section_element_selectors"&gt;Hello&amp;nbsp;&lt;A class="sub_section_element_selectors" href="https://community.intel.com/t5/user/viewprofilepage/user-id/324520" target="_blank"&gt;@fp5849&lt;/A&gt;,&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;The&amp;nbsp;&lt;SPAN&gt;JHL8440 has x4 PCIe TB4 but with the USB4 tunneled feature, the direct PCIe PHY is x1 lane TBT3. This decision could be a market decision being available the JHL7440.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;Best regards,&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&lt;A class="sub_section_element_selectors" href="https://community.intel.com/t5/user/viewprofilepage/user-id/266977?emcs_t=S2h8ZW1haWx8dG9waWNfc3Vic2NyaXB0aW9ufExMNDhLVVI2SDhQSlZTfDE1MTI2NTh8U1VCU0NSSVBUSU9OU3xoSw" target="_blank" rel="noopener"&gt;@Diego_INTEL&lt;/A&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Sat, 25 Nov 2023 00:50:57 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Connectivity/Questions-about-Thunderbolt-4-controller-specifications-and/m-p/1547326#M4903</guid>
      <dc:creator>Diego_INTEL</dc:creator>
      <dc:date>2023-11-25T00:50:57Z</dc:date>
    </item>
  </channel>
</rss>

