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    <title>topic Re: E810-XXVAM2 in Embedded Connectivity</title>
    <link>https://community.intel.com/t5/Embedded-Connectivity/E810-XXVAM2/m-p/1553179#M4980</link>
    <description>&lt;P&gt;Hi Diego,&lt;/P&gt;&lt;P&gt;I made a change to the driver that was given to me to use. I added the line ctxt-&amp;gt;info.inner_vlan_flags |= ICE_AQ_VSI_INNER_EMODE_NOTHING.&lt;/P&gt;&lt;P&gt;It solved the problem of NOT throwing away the incoming tags, but I have no idea as to why.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I started Searching thru the code that you suggested and did not show any results on using&amp;nbsp;ICE_AQ_VSI_INNER_EMODE_NOTHING.&lt;/P&gt;&lt;P&gt;I would really like to know why this line made the difference, However the device driver that was given to me is a half breed of Intel's driver for the E810.&amp;nbsp;&lt;/P&gt;&lt;P&gt;I think at this time frame I will close the issue, unless someone can shed light on ctxt-&amp;gt;info.inner_vlan_flags.&lt;/P&gt;</description>
    <pubDate>Tue, 12 Dec 2023 17:38:00 GMT</pubDate>
    <dc:creator>Greif</dc:creator>
    <dc:date>2023-12-12T17:38:00Z</dc:date>
    <item>
      <title>E810-XXVAM2</title>
      <link>https://community.intel.com/t5/Embedded-Connectivity/E810-XXVAM2/m-p/1550455#M4930</link>
      <description>&lt;P&gt;I AM trying to Deal with a tagged VLAN on a receive packet.&lt;/P&gt;&lt;P&gt;I am trying to control certain registers on the chip that will allow me to pass the receive packet with tag value without striping the tag.&amp;nbsp;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Any help would be appreciated. I am new to this E810 chip.&lt;/P&gt;&lt;P&gt;I have changed some fields, but I am still not getting any received messages. The incoming packet is a tag packet and I need to pass this packet thru without any stripping of the tag.&amp;nbsp;&lt;/P&gt;&lt;P&gt;I have set the Global Configuration (L2 Tag Control - GL_SWT_L2TAGCTRL[n]), Location 13.2.2.8.5 within the E810 document, to the following:&lt;/P&gt;&lt;TABLE&gt;&lt;TBODY&gt;&lt;TR&gt;&lt;TD width="342"&gt;&lt;P&gt;Global Configuration&lt;/P&gt;&lt;/TD&gt;&lt;TD width="74"&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/TD&gt;&lt;TD width="208"&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD width="342"&gt;&lt;P&gt;GL_SWT_L2TAGCTRL. ETHERTYPE&lt;/P&gt;&lt;/TD&gt;&lt;TD width="74"&gt;&lt;P&gt;0x8100&lt;/P&gt;&lt;/TD&gt;&lt;TD width="208"&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD width="342"&gt;&lt;P&gt;GL_SWT_L2TAGCTRL.ISVLAN&amp;nbsp;&amp;nbsp; 1&lt;/P&gt;&lt;/TD&gt;&lt;TD width="74"&gt;&lt;P&gt;1&lt;/P&gt;&lt;/TD&gt;&lt;TD width="208"&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD width="342"&gt;&lt;P&gt;PRT_L2TAGSEN.NON_LAST_TAG&lt;/P&gt;&lt;/TD&gt;&lt;TD width="74"&gt;&lt;P&gt;0&lt;/P&gt;&lt;/TD&gt;&lt;TD width="208"&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD width="342"&gt;&lt;P&gt;GL_SWT_L2TAGCTRL.INNERUP&lt;/P&gt;&lt;/TD&gt;&lt;TD width="74"&gt;&lt;P&gt;1&lt;/P&gt;&lt;/TD&gt;&lt;TD width="208"&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD width="342"&gt;&lt;P&gt;GL_SWT_L2TAGCTRL.OUTERUP&lt;/P&gt;&lt;/TD&gt;&lt;TD width="74"&gt;&lt;P&gt;0&lt;/P&gt;&lt;/TD&gt;&lt;TD width="208"&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD width="342"&gt;&lt;P&gt;GL_SWT_L2TAGCTRL.LONG&lt;/P&gt;&lt;/TD&gt;&lt;TD width="74"&gt;&lt;P&gt;0&lt;/P&gt;&lt;/TD&gt;&lt;TD width="208"&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD width="342"&gt;&lt;P&gt;GL_SWT_L2TAGCTRL.HAS_UP&lt;/P&gt;&lt;/TD&gt;&lt;TD width="74"&gt;&lt;P&gt;1&lt;/P&gt;&lt;/TD&gt;&lt;TD width="208"&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD width="342"&gt;&lt;P&gt;GL_SWT_L2TAGCTRL.ISMPLS&lt;/P&gt;&lt;/TD&gt;&lt;TD width="74"&gt;&lt;P&gt;0&lt;/P&gt;&lt;/TD&gt;&lt;TD width="208"&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD width="342"&gt;&lt;P&gt;GL_SWT_L2TAGCTRL.ISNSH&lt;/P&gt;&lt;/TD&gt;&lt;TD width="74"&gt;&lt;P&gt;0&lt;/P&gt;&lt;/TD&gt;&lt;TD width="208"&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD width="342"&gt;&lt;P&gt;GL_SWT_L2TAGCTRL.LENGTH&lt;/P&gt;&lt;/TD&gt;&lt;TD width="74"&gt;&lt;P&gt;2&lt;/P&gt;&lt;/TD&gt;&lt;TD width="208"&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD width="342"&gt;&lt;P&gt;GL_SWT_L2TAGTXIB.OFFSET&lt;/P&gt;&lt;/TD&gt;&lt;TD width="74"&gt;&lt;P&gt;0&lt;/P&gt;&lt;/TD&gt;&lt;TD width="208"&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD width="342"&gt;&lt;P&gt;GL_SWT_L2TAGTXIB.LENGTH&amp;nbsp; 3&lt;/P&gt;&lt;/TD&gt;&lt;TD width="74"&gt;&lt;P&gt;01b&lt;/P&gt;&lt;/TD&gt;&lt;TD width="208"&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD width="342"&gt;&lt;P&gt;GL_SWT_L2TAGRXEB.OFFSET&lt;/P&gt;&lt;/TD&gt;&lt;TD width="74"&gt;&lt;P&gt;0&lt;/P&gt;&lt;/TD&gt;&lt;TD width="208"&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD width="342"&gt;&lt;P&gt;GL_SWT_L2TAGRXEB.LENGTH&amp;nbsp;&amp;nbsp; 3&lt;/P&gt;&lt;/TD&gt;&lt;TD width="74"&gt;&lt;P&gt;01b&lt;/P&gt;&lt;/TD&gt;&lt;TD width="208"&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD width="342"&gt;&lt;P&gt;GL_SWT_L2TAGDATA0, GL_SWT_L2TAGDATA1&lt;/P&gt;&lt;/TD&gt;&lt;TD width="74"&gt;&lt;P&gt;All zeros&lt;/P&gt;&lt;/TD&gt;&lt;TD width="208"&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD width="342"&gt;&lt;P&gt;Per Port Configuration (Controlled by Set Port Parameters command)&lt;/P&gt;&lt;/TD&gt;&lt;TD width="74"&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/TD&gt;&lt;TD width="208"&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD width="342"&gt;&lt;P&gt;PRT_L2TAGSEN.ENABLE and&lt;/P&gt;&lt;P&gt;GL_L2TAGSEN_m_n (m= 0..3, n= 0..1)&lt;/P&gt;&lt;/TD&gt;&lt;TD width="74"&gt;&lt;P&gt;1&lt;/P&gt;&lt;/TD&gt;&lt;TD width="208"&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/TD&gt;&lt;/TR&gt;&lt;/TBODY&gt;&lt;/TABLE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;The E810 Datasheet section 7.12.3.3 states that the tag extraction rules are controlled by the following:&lt;/P&gt;&lt;P&gt;&amp;nbsp;VSI_TSR.STRIPTAG, VSI_TSR.SHOWTAG, and VSI_TSR.SHOWPRIONLY bit fields.&lt;/P&gt;&lt;P&gt;Within Table 7-290 Tag Extraction Example, the document talks about “SHOWIV and L2TSEL”:&lt;/P&gt;&lt;P&gt;We, have SHOWIV and L2TSEL set to a 1, 0 respectfully.&amp;nbsp; Which selects Inner VLAN on L2TAG1.&lt;/P&gt;&lt;P&gt;However, I believe this only pertains to different cases assuming the first tag is an STag and the second tag is a VLAN.&lt;/P&gt;&lt;P&gt;We don’t have a Stag only a typical 802.1 (8100) vlan tag.&lt;/P&gt;&lt;P&gt;If the VSI_TSR.STRIPTAG, VSI_TSR.SHOWTAG, and VSI_TSR.SHOWPRIONLY bit fields control the extraction rules how do you set this for “DO nothing” just leave the packet as is.&lt;/P&gt;&lt;P&gt;The setting is set as follows:&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;VSI_TSR Register&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;VSI_TSR.STRIPTAG = 0&lt;/P&gt;&lt;P&gt;SHOWTAG = 0&lt;/P&gt;&lt;P&gt;SHOWPRIONLY = 0&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;VSI_TAR Register&amp;nbsp; &amp;nbsp; per document 13.2.2.12.5&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;ACCEPTTAGGED = 0&lt;/P&gt;&lt;P&gt;ACCEPTUNTAGGED = 0&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;prt_tdpul2tagsen Register&amp;nbsp; &amp;nbsp;per document 13.2.2.26.1&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;Enable = 1&lt;/P&gt;&lt;P&gt;Not sure what Table 7-292 is really saying. We have eight incoming Ports attached to an external switch which delivers the packet and tag. I don't see how the GL_L2TAGSEN_0_0 comes into play.&lt;/P&gt;</description>
      <pubDate>Mon, 04 Dec 2023 23:10:29 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Connectivity/E810-XXVAM2/m-p/1550455#M4930</guid>
      <dc:creator>Greif</dc:creator>
      <dc:date>2023-12-04T23:10:29Z</dc:date>
    </item>
    <item>
      <title>Re: E810-XXVAM2</title>
      <link>https://community.intel.com/t5/Embedded-Connectivity/E810-XXVAM2/m-p/1552138#M4964</link>
      <description>&lt;P class="sub_section_element_selectors"&gt;Hello&amp;nbsp;&lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/326621"&gt;@Greif&lt;/a&gt;,&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&lt;SPAN class="sub_section_element_selectors"&gt;Thank you for contacting Intel Embedded Community.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;You can try asking in the Ethernet Products Community as here is only for Embedded Products.&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&lt;A href="https://community.intel.com/t5/Ethernet-Products/bd-p/ethernet-products" target="_blank"&gt;https://community.intel.com/t5/Ethernet-Products/bd-p/ethernet-products&lt;/A&gt;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;But I have been investigating on my own in our resources and could be a driver issue with ice, but I'm not entirely sure, you may try updating the driver to the latest release just in case.&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;Also, you can check these links:&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&lt;A href="https://github.com/torvalds/linux/commit/fe911c89756671fc553d8d67836a65151e04c4d7" target="_blank"&gt;https://github.com/torvalds/linux/commit/fe911c89756671fc553d8d67836a65151e04c4d7&lt;/A&gt;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&lt;A href="https://github.com/torvalds/linux/compare/master...mfijalko:linux:another61mbuf" target="_blank"&gt;https://github.com/torvalds/linux/compare/master...mfijalko:linux:another61mbuf&lt;/A&gt;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&lt;A href="https://github.com/mfijalko/linux/tree/another61mbuf" target="_blank"&gt;https://github.com/mfijalko/linux/tree/another61mbuf&lt;/A&gt;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&lt;BR /&gt;Best regards,&lt;BR /&gt;&lt;BR /&gt;&lt;A class="sub_section_element_selectors" href="https://community.intel.com/t5/user/viewprofilepage/user-id/266977" target="_blank" rel="noopener"&gt;@Diego_INTEL&lt;/A&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Sat, 09 Dec 2023 04:21:41 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Connectivity/E810-XXVAM2/m-p/1552138#M4964</guid>
      <dc:creator>Diego_INTEL</dc:creator>
      <dc:date>2023-12-09T04:21:41Z</dc:date>
    </item>
    <item>
      <title>Re: E810-XXVAM2</title>
      <link>https://community.intel.com/t5/Embedded-Connectivity/E810-XXVAM2/m-p/1553179#M4980</link>
      <description>&lt;P&gt;Hi Diego,&lt;/P&gt;&lt;P&gt;I made a change to the driver that was given to me to use. I added the line ctxt-&amp;gt;info.inner_vlan_flags |= ICE_AQ_VSI_INNER_EMODE_NOTHING.&lt;/P&gt;&lt;P&gt;It solved the problem of NOT throwing away the incoming tags, but I have no idea as to why.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I started Searching thru the code that you suggested and did not show any results on using&amp;nbsp;ICE_AQ_VSI_INNER_EMODE_NOTHING.&lt;/P&gt;&lt;P&gt;I would really like to know why this line made the difference, However the device driver that was given to me is a half breed of Intel's driver for the E810.&amp;nbsp;&lt;/P&gt;&lt;P&gt;I think at this time frame I will close the issue, unless someone can shed light on ctxt-&amp;gt;info.inner_vlan_flags.&lt;/P&gt;</description>
      <pubDate>Tue, 12 Dec 2023 17:38:00 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Connectivity/E810-XXVAM2/m-p/1553179#M4980</guid>
      <dc:creator>Greif</dc:creator>
      <dc:date>2023-12-12T17:38:00Z</dc:date>
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