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  <channel>
    <title>topic Re: Re:Using x16 pcie slot disables low package c states ASPM. Alderlake and Raptorlake in Embedded Connectivity</title>
    <link>https://community.intel.com/t5/Embedded-Connectivity/Using-x16-pcie-slot-disables-low-package-c-states-ASPM-Alderlake/m-p/1556971#M5027</link>
    <description>&lt;P class="sub_section_element_selectors"&gt;Hello&amp;nbsp;&lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/272677"&gt;@etnivor&lt;/a&gt;,&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&lt;SPAN class="sub_section_element_selectors"&gt;Thank you for contacting Intel Embedded Community.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;I have been investigating and it seems that it can be fixed from the BIOS, internally I have found this recommendation that worked in Gen 12th and Gen 13th.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;"In your BIOS:&lt;/P&gt;
&lt;P&gt;Advanced -&amp;gt; Admin -&amp;gt; Chipset-&amp;gt;System Agent(SA) configuration-&amp;gt;PCI Express Configuration&lt;/P&gt;
&lt;P&gt;Set Multi-VC to Disabled on both of PCIE Root Port 1 &amp;amp; PCIE Root Port 2."&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;Setting&amp;nbsp;Multi-VC to Disabled could help reaching C10, meanwhile, by being enabled, the system can only reach C3.&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;Also, that link that you have shared was very useful.&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;I hope this helps in your case.&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&lt;BR /&gt;Best regards,&lt;BR /&gt;&lt;BR /&gt;&lt;A class="sub_section_element_selectors" href="https://community.intel.com/t5/user/viewprofilepage/user-id/266977" target="_blank" rel="noopener"&gt;@Diego_INTEL&lt;/A&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Sat, 23 Dec 2023 03:56:25 GMT</pubDate>
    <dc:creator>Diego_INTEL</dc:creator>
    <dc:date>2023-12-23T03:56:25Z</dc:date>
    <item>
      <title>Using x16 pcie slot disables low package c states ASPM. Alderlake and Raptorlake</title>
      <link>https://community.intel.com/t5/Embedded-Connectivity/Using-x16-pcie-slot-disables-low-package-c-states-ASPM-Alderlake/m-p/1555031#M5012</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;I have a question regarding using INTEL X710-DA2(pcie gen3, x8) in pcie slot 1 which connects directly to cpu.&lt;/P&gt;&lt;P&gt;Is it a design choice to prevent cpu to go to lower package C states when using x16 slot connected directly to cpu?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I have a Asus B760 motherboard with an i3-13100, where if I use the x16 slot cpu package state gets limited to c3.&lt;/P&gt;&lt;P&gt;However if I connect the X710-Da2 to x4 slot to south bridge it all works and my package states goes down to c6.(Card gets limited by the 4x lane though)&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I have a chinese mini itx motherboard with an i5-12500H cpu and it has the same issue. Although it only has the x16 slot. I have modded the BIOS and have given me full access to all configuration options, but unable to make it work.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I found a "blogpost" on H770 motherboard which reports the same issues I have using x16 slot.&lt;/P&gt;&lt;P&gt;&lt;A href="https://mattgadient.com/7-watts-idle-on-intel-12th-13th-gen-the-foundation-for-building-a-low-power-server-nas/" target="_blank" rel="noopener"&gt;https://mattgadient.com/7-watts-idle-on-intel-12th-13th-gen-the-foundation-for-building-a-low-power-server-nas/&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Is this a design in hardware(CPU) or is it a firmware(BIOS) issue? Can I do anything to make it work?&lt;/P&gt;</description>
      <pubDate>Mon, 18 Dec 2023 12:06:24 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Connectivity/Using-x16-pcie-slot-disables-low-package-c-states-ASPM-Alderlake/m-p/1555031#M5012</guid>
      <dc:creator>etnivor</dc:creator>
      <dc:date>2023-12-18T12:06:24Z</dc:date>
    </item>
    <item>
      <title>Re:Using x16 pcie slot disables low package c states ASPM. Alderlake and Raptorlake</title>
      <link>https://community.intel.com/t5/Embedded-Connectivity/Using-x16-pcie-slot-disables-low-package-c-states-ASPM-Alderlake/m-p/1555738#M5013</link>
      <description>&lt;P&gt;Hello etnivor,&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;I do appreciate that you took the time to post in our community forum. I would like to let you know that we have a thread for this kind of inquiry, and a specialist will get in contact with you as soon as possible.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Thanks for your comprehension.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Best regards,&amp;nbsp;&lt;/P&gt;&lt;P&gt;Deivid A.&amp;nbsp;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Intel Customer Support Technician&amp;nbsp;&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Tue, 19 Dec 2023 22:55:00 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Connectivity/Using-x16-pcie-slot-disables-low-package-c-states-ASPM-Alderlake/m-p/1555738#M5013</guid>
      <dc:creator>DeividA_Intel</dc:creator>
      <dc:date>2023-12-19T22:55:00Z</dc:date>
    </item>
    <item>
      <title>Re:Using x16 pcie slot disables low package c states ASPM. Alderlake and Raptorlake</title>
      <link>https://community.intel.com/t5/Embedded-Connectivity/Using-x16-pcie-slot-disables-low-package-c-states-ASPM-Alderlake/m-p/1555837#M5014</link>
      <description>&lt;P&gt;Greetings,&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Thank you for contacting Intel Customer Support.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;We have a dedicated team to support your queries, hence we will transfer to embedded community team.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Additionally, you may create IPS case if you have the Intel Premier Account support.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Ryo&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Wed, 20 Dec 2023 08:57:16 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Connectivity/Using-x16-pcie-slot-disables-low-package-c-states-ASPM-Alderlake/m-p/1555837#M5014</guid>
      <dc:creator>Yogaeasvaran</dc:creator>
      <dc:date>2023-12-20T08:57:16Z</dc:date>
    </item>
    <item>
      <title>Re: Re:Using x16 pcie slot disables low package c states ASPM. Alderlake and Raptorlake</title>
      <link>https://community.intel.com/t5/Embedded-Connectivity/Using-x16-pcie-slot-disables-low-package-c-states-ASPM-Alderlake/m-p/1556212#M5019</link>
      <description>&lt;P&gt;Thankyou.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Do not have any premier account, awaiting response from embedded team.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Cheers&lt;/P&gt;</description>
      <pubDate>Thu, 21 Dec 2023 07:35:26 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Connectivity/Using-x16-pcie-slot-disables-low-package-c-states-ASPM-Alderlake/m-p/1556212#M5019</guid>
      <dc:creator>etnivor</dc:creator>
      <dc:date>2023-12-21T07:35:26Z</dc:date>
    </item>
    <item>
      <title>Re: Re:Using x16 pcie slot disables low package c states ASPM. Alderlake and Raptorlake</title>
      <link>https://community.intel.com/t5/Embedded-Connectivity/Using-x16-pcie-slot-disables-low-package-c-states-ASPM-Alderlake/m-p/1556971#M5027</link>
      <description>&lt;P class="sub_section_element_selectors"&gt;Hello&amp;nbsp;&lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/272677"&gt;@etnivor&lt;/a&gt;,&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&lt;SPAN class="sub_section_element_selectors"&gt;Thank you for contacting Intel Embedded Community.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;I have been investigating and it seems that it can be fixed from the BIOS, internally I have found this recommendation that worked in Gen 12th and Gen 13th.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;"In your BIOS:&lt;/P&gt;
&lt;P&gt;Advanced -&amp;gt; Admin -&amp;gt; Chipset-&amp;gt;System Agent(SA) configuration-&amp;gt;PCI Express Configuration&lt;/P&gt;
&lt;P&gt;Set Multi-VC to Disabled on both of PCIE Root Port 1 &amp;amp; PCIE Root Port 2."&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;Setting&amp;nbsp;Multi-VC to Disabled could help reaching C10, meanwhile, by being enabled, the system can only reach C3.&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;Also, that link that you have shared was very useful.&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;I hope this helps in your case.&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&lt;BR /&gt;Best regards,&lt;BR /&gt;&lt;BR /&gt;&lt;A class="sub_section_element_selectors" href="https://community.intel.com/t5/user/viewprofilepage/user-id/266977" target="_blank" rel="noopener"&gt;@Diego_INTEL&lt;/A&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Sat, 23 Dec 2023 03:56:25 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Connectivity/Using-x16-pcie-slot-disables-low-package-c-states-ASPM-Alderlake/m-p/1556971#M5027</guid>
      <dc:creator>Diego_INTEL</dc:creator>
      <dc:date>2023-12-23T03:56:25Z</dc:date>
    </item>
    <item>
      <title>Re: Using x16 pcie slot disables low package c states ASPM. Alderlake and Raptorlake</title>
      <link>https://community.intel.com/t5/Embedded-Connectivity/Using-x16-pcie-slot-disables-low-package-c-states-ASPM-Alderlake/m-p/1557028#M5029</link>
      <description>&lt;P&gt;Thankyou,&lt;/P&gt;&lt;P&gt;will try this on my i5-12500h board when back home after x-mas.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Don't have access to those settings on my Asus board. Will have to mod the Asus bios aswell.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Merry X-mas&lt;/P&gt;</description>
      <pubDate>Sat, 23 Dec 2023 17:33:17 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Connectivity/Using-x16-pcie-slot-disables-low-package-c-states-ASPM-Alderlake/m-p/1557028#M5029</guid>
      <dc:creator>etnivor</dc:creator>
      <dc:date>2023-12-23T17:33:17Z</dc:date>
    </item>
    <item>
      <title>Re: Re:Using x16 pcie slot disables low package c states ASPM. Alderlake and Raptorlake</title>
      <link>https://community.intel.com/t5/Embedded-Connectivity/Using-x16-pcie-slot-disables-low-package-c-states-ASPM-Alderlake/m-p/1558841#M5033</link>
      <description>&lt;P&gt;Hello again,&lt;/P&gt;&lt;P&gt;tried disabling Multi-VC on my Erying i5-12500h motherboard. No luck there, also tried switching to an Intel I226-V nic but same issue. Actually only reach C2 when using x16 slot.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;No luck modding Asus bios would need to mod cap file and don't have the tooling todo that. So can not test on the Asus MB.&lt;/P&gt;&lt;P&gt;Cheers.&lt;/P&gt;</description>
      <pubDate>Mon, 01 Jan 2024 12:27:14 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Connectivity/Using-x16-pcie-slot-disables-low-package-c-states-ASPM-Alderlake/m-p/1558841#M5033</guid>
      <dc:creator>etnivor</dc:creator>
      <dc:date>2024-01-01T12:27:14Z</dc:date>
    </item>
    <item>
      <title>Re: Re:Using x16 pcie slot disables low package c states ASPM. Alderlake and Raptorlake</title>
      <link>https://community.intel.com/t5/Embedded-Connectivity/Using-x16-pcie-slot-disables-low-package-c-states-ASPM-Alderlake/m-p/1559081#M5035</link>
      <description>&lt;P&gt;Hello again Diego.&lt;/P&gt;&lt;P&gt;may I ask where I can download Intel FPT tool ?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;BR&lt;/P&gt;&lt;P&gt;Nils&lt;/P&gt;</description>
      <pubDate>Tue, 02 Jan 2024 12:24:07 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Connectivity/Using-x16-pcie-slot-disables-low-package-c-states-ASPM-Alderlake/m-p/1559081#M5035</guid>
      <dc:creator>etnivor</dc:creator>
      <dc:date>2024-01-02T12:24:07Z</dc:date>
    </item>
    <item>
      <title>Re: Re:Using x16 pcie slot disables low package c states ASPM. Alderlake and Raptorlake</title>
      <link>https://community.intel.com/t5/Embedded-Connectivity/Using-x16-pcie-slot-disables-low-package-c-states-ASPM-Alderlake/m-p/1559659#M5038</link>
      <description>&lt;DIV id="bodyDisplay_3" class="lia-message-body lia-component-message-view-widget-body lia-component-body-signature-highlight-escalation lia-component-message-view-widget-body-signature-highlight-escalation section_selectors" data-section_field_id="1e39-f176-6e28"&gt;
&lt;DIV class="lia-message-body-content sub_section_element_selectors"&gt;
&lt;P class="sub_section_element_selectors"&gt;Hello&amp;nbsp;&lt;A class="sub_section_element_selectors" href="https://community.intel.com/t5/user/viewprofilepage/user-id/272677" target="_blank"&gt;@etnivor&lt;/A&gt;,&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;The FPT can be accessed in one document related to the family's processor, in this case, Alder Lake or Raptor Lake, but you will need a Premier account in order to get access to this document.&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;For example, document #781359 in RDC.&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;Also, you can check this article:&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;How to Apply for an Intel® Resource and Documentation Center (RDC) and/or Intel® Developer Zone (Intel® DevZone) Account&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&lt;A href="https://www.intel.com/content/www/us/en/support/articles/000058073/programs/resource-and-documentation-center.html" target="_blank"&gt;https://www.intel.com/content/www/us/en/support/articles/000058073/programs/resource-and-documentation-center.html&lt;/A&gt;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&lt;BR /&gt;Best regards,&lt;BR /&gt;&lt;BR /&gt;&lt;A class="sub_section_element_selectors" href="https://community.intel.com/t5/user/viewprofilepage/user-id/266977" target="_blank" rel="noopener"&gt;@Diego_INTEL&lt;/A&gt;&lt;/P&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;</description>
      <pubDate>Wed, 03 Jan 2024 23:08:06 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Connectivity/Using-x16-pcie-slot-disables-low-package-c-states-ASPM-Alderlake/m-p/1559659#M5038</guid>
      <dc:creator>Diego_INTEL</dc:creator>
      <dc:date>2024-01-03T23:08:06Z</dc:date>
    </item>
    <item>
      <title>Re: Re:Using x16 pcie slot disables low package c states ASPM. Alderlake and Raptorlake</title>
      <link>https://community.intel.com/t5/Embedded-Connectivity/Using-x16-pcie-slot-disables-low-package-c-states-ASPM-Alderlake/m-p/1561112#M5055</link>
      <description>&lt;P&gt;Thx,&lt;/P&gt;&lt;P&gt;yes found out CSME tooling wasn't publically available.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Have ordered a flash programmer, should get it at end of month. Then I should be able to mod Asus bios. Will update how it went with Asus board then &lt;LI-EMOJI id="lia_slightly-smiling-face" title=":slightly_smiling_face:"&gt;&lt;/LI-EMOJI&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Cheers&lt;/P&gt;</description>
      <pubDate>Tue, 09 Jan 2024 10:57:32 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Connectivity/Using-x16-pcie-slot-disables-low-package-c-states-ASPM-Alderlake/m-p/1561112#M5055</guid>
      <dc:creator>etnivor</dc:creator>
      <dc:date>2024-01-09T10:57:32Z</dc:date>
    </item>
    <item>
      <title>Re: Re:Using x16 pcie slot disables low package c states ASPM. Alderlake and Raptorlake</title>
      <link>https://community.intel.com/t5/Embedded-Connectivity/Using-x16-pcie-slot-disables-low-package-c-states-ASPM-Alderlake/m-p/1572686#M5169</link>
      <description>&lt;P&gt;Hello Diego,&lt;/P&gt;&lt;P&gt;took some time until I got around. Had to desolder bios etc.. but have now gotten access to pcie root port settings on my motherboard.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;It kind of worked disabling multi-VC on root port 1.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;It does not work with the Intel X710-Da2 nic for some reason. Only get to C2.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;However it work with an Asmedia1166 pcie sata card, where I get down to c8 which previously only got to c3.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I guess this is an ok solution for me since I can run the x710-da2 nic on an x4 lane pcie slot on southbridge. Unless you have some other tweak I can try &lt;LI-EMOJI id="lia_grinning-face-with-big-eyes" title=":grinning_face_with_big_eyes:"&gt;&lt;/LI-EMOJI&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 15 Feb 2024 20:12:22 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Connectivity/Using-x16-pcie-slot-disables-low-package-c-states-ASPM-Alderlake/m-p/1572686#M5169</guid>
      <dc:creator>etnivor</dc:creator>
      <dc:date>2024-02-15T20:12:22Z</dc:date>
    </item>
    <item>
      <title>Re: Re:Using x16 pcie slot disables low package c states ASPM. Alderlake and Raptorlake</title>
      <link>https://community.intel.com/t5/Embedded-Connectivity/Using-x16-pcie-slot-disables-low-package-c-states-ASPM-Alderlake/m-p/1573063#M5178</link>
      <description>&lt;P class="sub_section_element_selectors"&gt;Hello&amp;nbsp;&lt;A class="sub_section_element_selectors" href="https://community.intel.com/t5/user/viewprofilepage/user-id/272677" target="_blank" rel="noopener"&gt;@etnivor&lt;/A&gt;,&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;Yes, that was the only fix I could find, I'm glad that it could help in one board at least, I'm not sure if the design of the other board may affect, there is a different design for deep sleep states, could be the case.&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&lt;BR /&gt;Best regards,&lt;BR /&gt;&lt;BR /&gt;&lt;A class="sub_section_element_selectors" href="https://community.intel.com/t5/user/viewprofilepage/user-id/266977" target="_blank" rel="noopener"&gt;@Diego_INTEL&lt;/A&gt;&lt;/P&gt;</description>
      <pubDate>Sat, 17 Feb 2024 04:19:40 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Connectivity/Using-x16-pcie-slot-disables-low-package-c-states-ASPM-Alderlake/m-p/1573063#M5178</guid>
      <dc:creator>Diego_INTEL</dc:creator>
      <dc:date>2024-02-17T04:19:40Z</dc:date>
    </item>
    <item>
      <title>Re: Re:Using x16 pcie slot disables low package c states ASPM. Alderlake and Raptorlake</title>
      <link>https://community.intel.com/t5/Embedded-Connectivity/Using-x16-pcie-slot-disables-low-package-c-states-ASPM-Alderlake/m-p/1740350#M5946</link>
      <description>&lt;P&gt;Hello Diego&lt;BR /&gt;&lt;BR /&gt;I found your post very intresting because i go an i9-13900 with a ROG STRIX Z690-A GAMING WIFI (Rev. 1xx) and can't find under System Agent(SA) configuration -&amp;gt;PCI Express Configuration a button to disable Multi-VC on PCIE Root Port 1 &amp;amp; PCIE Root Port 2.&lt;BR /&gt;&lt;BR /&gt;Bevor i got an i3-13100 with an other Motherboard from Asus, but with the same Problem...&lt;BR /&gt;What can I do? Do I need custom BIOS firmware to handle multi-VC? I'm very frustrated....&lt;BR /&gt;&lt;BR /&gt;Best Regards&lt;BR /&gt;&lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/475696"&gt;@fanta989&lt;/a&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 10 Mar 2026 10:25:45 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Connectivity/Using-x16-pcie-slot-disables-low-package-c-states-ASPM-Alderlake/m-p/1740350#M5946</guid>
      <dc:creator>fanta989</dc:creator>
      <dc:date>2026-03-10T10:25:45Z</dc:date>
    </item>
    <item>
      <title>Re: Re:Using x16 pcie slot disables low package c states ASPM. Alderlake and Raptorlake</title>
      <link>https://community.intel.com/t5/Embedded-Connectivity/Using-x16-pcie-slot-disables-low-package-c-states-ASPM-Alderlake/m-p/1740359#M5947</link>
      <description>&lt;P&gt;I had to desolder bios from motherboard and dump it and modify it and flash it back.&lt;/P&gt;&lt;P&gt;I used uefi editor to modify it.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;It's possible to modify BIOS in-place but was way to much work and you needed access to none public software.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;You will never reach ASUS engineers.&lt;/P&gt;</description>
      <pubDate>Tue, 10 Mar 2026 12:15:24 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Connectivity/Using-x16-pcie-slot-disables-low-package-c-states-ASPM-Alderlake/m-p/1740359#M5947</guid>
      <dc:creator>etnivor</dc:creator>
      <dc:date>2026-03-10T12:15:24Z</dc:date>
    </item>
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