https://community.intel.com/t5/Ethernet-Products/82599-EICR-bits/m-p/523723#M10593 <P>Hi,</P><P></P><P>I'm trying to understand the 82599 chip, and I'd have a question concerning interrupts.</P><P>The data sheet (Revision: 2.74) marks bit 31 in EICR as "reserved", but the Linux driver</P><P>source defines it as</P><P># define IXGBE_EICR_OTHER 0x80000000 /* Interrupt Cause Active */</P><P>I saw in the interrupt service routine that sometimes this bit is set when an interrupt</P><P>occurs, and sometimes it is reset. This applies to the same cause, for example</P><P>link status change (LSC).</P><P>Can somebody explain the meaning of this bit?</P><P></P><P>Thanks</P><P>Gunter</P> Wed, 29 Feb 2012 13:27:59 GMT GKnit 2012-02-29T13:27:59Z https://community.intel.com/t5/Ethernet-Products/82599-EICR-bits/m-p/523723#M10593 <P>Hi,</P><P></P><P>I'm trying to understand the 82599 chip, and I'd have a question concerning interrupts.</P><P>The data sheet (Revision: 2.74) marks bit 31 in EICR as "reserved", but the Linux driver</P><P>source defines it as</P><P># define IXGBE_EICR_OTHER 0x80000000 /* Interrupt Cause Active */</P><P>I saw in the interrupt service routine that sometimes this bit is set when an interrupt</P><P>occurs, and sometimes it is reset. This applies to the same cause, for example</P><P>link status change (LSC).</P><P>Can somebody explain the meaning of this bit?</P><P></P><P>Thanks</P><P>Gunter</P> Wed, 29 Feb 2012 13:27:59 GMT https://community.intel.com/t5/Ethernet-Products/82599-EICR-bits/m-p/523723#M10593 GKnit 2012-02-29T13:27:59Z