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    <title>topic Re:Tofino 3 Details/Match-Action Table Clarification in Ethernet Products</title>
    <link>https://community.intel.com/t5/Ethernet-Products/Tofino-3-Details-Match-Action-Table-Clarification/m-p/1436628#M31409</link>
    <description>&lt;P&gt;Hello ThePuriProdigy,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I hope you're having a wonderful day. I am just sending a soft follow up on the information that we requested for us to further assist you. We will wait for your reply.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;If you have questions, please let us know. In case we do not hear from you, we will make a follow up after 3 workings days. Thank you.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Michael L.&lt;/P&gt;&lt;P&gt;Intel® Customer Support&lt;/P&gt;&lt;BR /&gt;</description>
    <pubDate>Wed, 07 Dec 2022 22:42:12 GMT</pubDate>
    <dc:creator>Mike_Intel</dc:creator>
    <dc:date>2022-12-07T22:42:12Z</dc:date>
    <item>
      <title>Tofino 3 Details/Match-Action Table Clarification</title>
      <link>https://community.intel.com/t5/Ethernet-Products/Tofino-3-Details-Match-Action-Table-Clarification/m-p/1435135#M31344</link>
      <description>&lt;P class="sub_section_element_selectors"&gt;&lt;SPAN class="sub_section_element_selectors"&gt;Hi all&lt;/SPAN&gt;&lt;SPAN class="sub_section_element_selectors"&gt;,&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;SPAN class="sub_section_element_selectors"&gt;a common way I see pipeline architectures in devices such as the Tofino 3 switch that contain MAU units defined is each MAU has x TCAM blocks and y SRAM pages. Are the x and y amounts of TCAM/SRAM referring to the amount available solely for the key portion of a key, action, action data table? As an example, if an MAU is described as having 100 SRAM pages available and my algorithm will use 100 SRAM pages worth of keys + additional 20 pages for the action data, is that fine? Or will the action data SRAM amount also need to be factored in so that the key+action data will not exceed 100 pages total?&lt;/SPAN&gt;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&lt;SPAN class="sub_section_element_selectors"&gt;Also, I was wondering if there was a way to find out specific Tofino 3 specs such as the number of MAUs per pipeline and the amount of TCAM blocks/SRAM pages that they each hold?&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Fri, 02 Dec 2022 07:54:23 GMT</pubDate>
      <guid>https://community.intel.com/t5/Ethernet-Products/Tofino-3-Details-Match-Action-Table-Clarification/m-p/1435135#M31344</guid>
      <dc:creator>ThePuriProdigy</dc:creator>
      <dc:date>2022-12-02T07:54:23Z</dc:date>
    </item>
    <item>
      <title>Re:Tofino 3 Details/Match-Action Table Clarification</title>
      <link>https://community.intel.com/t5/Ethernet-Products/Tofino-3-Details-Match-Action-Table-Clarification/m-p/1435599#M31365</link>
      <description>&lt;P&gt;Hello ThePuriProdigy,&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Thank you for posting in Intel Ethernet Communities.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;For us to further check the issue, please provide the following details.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;What is the model of the Intel network card that you are using?&lt;/LI&gt;&lt;LI&gt;Can you share screen capture of the issue?&lt;/LI&gt;&lt;LI&gt;Are you designing a board/system with embedded Intel NIC?&lt;/LI&gt;&lt;LI&gt;Can you share more details about your inquiry?&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;If you have questions, please let us know. In case we do not hear from you, we will make a follow up after 3 workings days. Thank you.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Michael L.&lt;/P&gt;&lt;P&gt;Intel® Customer Support&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Mon, 05 Dec 2022 01:00:24 GMT</pubDate>
      <guid>https://community.intel.com/t5/Ethernet-Products/Tofino-3-Details-Match-Action-Table-Clarification/m-p/1435599#M31365</guid>
      <dc:creator>Mike_Intel</dc:creator>
      <dc:date>2022-12-05T01:00:24Z</dc:date>
    </item>
    <item>
      <title>Re:Tofino 3 Details/Match-Action Table Clarification</title>
      <link>https://community.intel.com/t5/Ethernet-Products/Tofino-3-Details-Match-Action-Table-Clarification/m-p/1436628#M31409</link>
      <description>&lt;P&gt;Hello ThePuriProdigy,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I hope you're having a wonderful day. I am just sending a soft follow up on the information that we requested for us to further assist you. We will wait for your reply.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;If you have questions, please let us know. In case we do not hear from you, we will make a follow up after 3 workings days. Thank you.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Michael L.&lt;/P&gt;&lt;P&gt;Intel® Customer Support&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Wed, 07 Dec 2022 22:42:12 GMT</pubDate>
      <guid>https://community.intel.com/t5/Ethernet-Products/Tofino-3-Details-Match-Action-Table-Clarification/m-p/1436628#M31409</guid>
      <dc:creator>Mike_Intel</dc:creator>
      <dc:date>2022-12-07T22:42:12Z</dc:date>
    </item>
    <item>
      <title>Re:Tofino 3 Details/Match-Action Table Clarification</title>
      <link>https://community.intel.com/t5/Ethernet-Products/Tofino-3-Details-Match-Action-Table-Clarification/m-p/1437899#M31463</link>
      <description>&lt;P&gt;Hello ThePuriProdigy,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I hope this message finds you well. I am just sending another follow up on the information that I requested. Since we have not heard back from you, I need to close this inquiry.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;If you need any additional information, please submit a new question as this thread will no longer be monitored.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Thank you and stay safe.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Michael L.&lt;/P&gt;&lt;P&gt;Intel® Customer Support&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Mon, 12 Dec 2022 22:46:23 GMT</pubDate>
      <guid>https://community.intel.com/t5/Ethernet-Products/Tofino-3-Details-Match-Action-Table-Clarification/m-p/1437899#M31463</guid>
      <dc:creator>Mike_Intel</dc:creator>
      <dc:date>2022-12-12T22:46:23Z</dc:date>
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