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    <title>topic using the hps phy via loanios from fpga (de10-nano-soc) in Ethernet Products</title>
    <link>https://community.intel.com/t5/Ethernet-Products/using-the-hps-phy-via-loanios-from-fpga-de10-nano-soc/m-p/198483#M376</link>
    <description>&lt;P&gt;Hi everybody,&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&amp;nbsp;&lt;P&gt;&lt;/P&gt;I'm currently struggling to access the hps ethernet phy from fpga. I followed this (&lt;A href="http://www.alterawiki.com/wiki/file:hpsio_demo.qar"&gt;http://www.alterawiki.com/wiki/file:hpsio_demo.qar&lt;/A&gt;) example. &amp;nbsp;&lt;P&gt;&lt;/P&gt;I need to configure the phy (&lt;A href="http://ww1.microchip.com/downloads/en/devicedoc/00002117f.pdf"&gt;http://ww1.microchip.com/downloads/en/devicedoc/00002117f.pdf&lt;/A&gt;) using the mdio and mdc pins. However, when i mux the loanio &amp;nbsp;&lt;P&gt;&lt;/P&gt;pins in qsys:&amp;nbsp;&lt;P&gt;&lt;/P&gt;&lt;A href="https://alteraforum.com/forum/attachment.php?attachmentid=14445&amp;amp;stc=1"&gt;https://alteraforum.com/forum/attachment.php?attachmentid=14445&amp;amp;stc=1&lt;/A&gt; &amp;nbsp;&lt;P&gt;&lt;/P&gt;And try to assign my 50MHz clock to them from my toplevel:&amp;nbsp;&lt;P&gt;&lt;/P&gt;&lt;A href="https://alteraforum.com/forum/attachment.php?attachmentid=14446&amp;amp;stc=1"&gt;https://alteraforum.com/forum/attachment.php?attachmentid=14446&amp;amp;stc=1&lt;/A&gt; &amp;nbsp;&lt;P&gt;&lt;/P&gt;When probing the phy pins using an oscilloscope, I do not see my 50Mhz clock as routed &amp;nbsp;&lt;P&gt;&lt;/P&gt;in the toplevel. On the contrary I see regular mdio accesses from somewhere.&amp;nbsp;&lt;P&gt;&lt;/P&gt;&amp;nbsp;&lt;P&gt;&lt;/P&gt;What am I doing wrong?&amp;nbsp;&lt;P&gt;&lt;/P&gt;&amp;nbsp;&lt;P&gt;&lt;/P&gt;EDIT: SOLVED! you need to generate preloader using bsp-editor, then use alt-boot-disk-util to flash to sd card</description>
    <pubDate>Tue, 21 Nov 2017 23:53:51 GMT</pubDate>
    <dc:creator>Altera_Forum</dc:creator>
    <dc:date>2017-11-21T23:53:51Z</dc:date>
    <item>
      <title>using the hps phy via loanios from fpga (de10-nano-soc)</title>
      <link>https://community.intel.com/t5/Ethernet-Products/using-the-hps-phy-via-loanios-from-fpga-de10-nano-soc/m-p/198483#M376</link>
      <description>&lt;P&gt;Hi everybody,&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&amp;nbsp;&lt;P&gt;&lt;/P&gt;I'm currently struggling to access the hps ethernet phy from fpga. I followed this (&lt;A href="http://www.alterawiki.com/wiki/file:hpsio_demo.qar"&gt;http://www.alterawiki.com/wiki/file:hpsio_demo.qar&lt;/A&gt;) example. &amp;nbsp;&lt;P&gt;&lt;/P&gt;I need to configure the phy (&lt;A href="http://ww1.microchip.com/downloads/en/devicedoc/00002117f.pdf"&gt;http://ww1.microchip.com/downloads/en/devicedoc/00002117f.pdf&lt;/A&gt;) using the mdio and mdc pins. However, when i mux the loanio &amp;nbsp;&lt;P&gt;&lt;/P&gt;pins in qsys:&amp;nbsp;&lt;P&gt;&lt;/P&gt;&lt;A href="https://alteraforum.com/forum/attachment.php?attachmentid=14445&amp;amp;stc=1"&gt;https://alteraforum.com/forum/attachment.php?attachmentid=14445&amp;amp;stc=1&lt;/A&gt; &amp;nbsp;&lt;P&gt;&lt;/P&gt;And try to assign my 50MHz clock to them from my toplevel:&amp;nbsp;&lt;P&gt;&lt;/P&gt;&lt;A href="https://alteraforum.com/forum/attachment.php?attachmentid=14446&amp;amp;stc=1"&gt;https://alteraforum.com/forum/attachment.php?attachmentid=14446&amp;amp;stc=1&lt;/A&gt; &amp;nbsp;&lt;P&gt;&lt;/P&gt;When probing the phy pins using an oscilloscope, I do not see my 50Mhz clock as routed &amp;nbsp;&lt;P&gt;&lt;/P&gt;in the toplevel. On the contrary I see regular mdio accesses from somewhere.&amp;nbsp;&lt;P&gt;&lt;/P&gt;&amp;nbsp;&lt;P&gt;&lt;/P&gt;What am I doing wrong?&amp;nbsp;&lt;P&gt;&lt;/P&gt;&amp;nbsp;&lt;P&gt;&lt;/P&gt;EDIT: SOLVED! you need to generate preloader using bsp-editor, then use alt-boot-disk-util to flash to sd card</description>
      <pubDate>Tue, 21 Nov 2017 23:53:51 GMT</pubDate>
      <guid>https://community.intel.com/t5/Ethernet-Products/using-the-hps-phy-via-loanios-from-fpga-de10-nano-soc/m-p/198483#M376</guid>
      <dc:creator>Altera_Forum</dc:creator>
      <dc:date>2017-11-21T23:53:51Z</dc:date>
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