https://community.intel.com/t5/Items-with-no-label/PCI-bridges-and-configuration-address-space/m-p/653049#M15002 <P>Hi,</P><P>I was trying to understand a PCI hierarchy with lspci when some questions came to me.</P><P>I had never really thought of it, but PCI bridges still have one configuration space, right? and only one device:bus:function address, right?</P><P>So my first question would be, which side of the bridge does that information refer to? the upstream or the downstream?</P><P>Also in the same line, but moving more to PCIe specifically, what side of the bridge is the information in the PCIe capabilitiy structure refering to? I mean we have a Link Capabilities for example, which tells us how fast that port can go, but what side is that info refering to?</P><P>I suspect I am thinking about this wrong but I can't see how, could someone enlighten me?</P><P>&nbsp;</P><P>Thanks!</P><P>-Albert.</P> Fri, 15 May 2020 08:48:47 GMT AArqu 2020-05-15T08:48:47Z https://community.intel.com/t5/Items-with-no-label/PCI-bridges-and-configuration-address-space/m-p/653049#M15002 <P>Hi,</P><P>I was trying to understand a PCI hierarchy with lspci when some questions came to me.</P><P>I had never really thought of it, but PCI bridges still have one configuration space, right? and only one device:bus:function address, right?</P><P>So my first question would be, which side of the bridge does that information refer to? the upstream or the downstream?</P><P>Also in the same line, but moving more to PCIe specifically, what side of the bridge is the information in the PCIe capabilitiy structure refering to? I mean we have a Link Capabilities for example, which tells us how fast that port can go, but what side is that info refering to?</P><P>I suspect I am thinking about this wrong but I can't see how, could someone enlighten me?</P><P>&nbsp;</P><P>Thanks!</P><P>-Albert.</P> Fri, 15 May 2020 08:48:47 GMT https://community.intel.com/t5/Items-with-no-label/PCI-bridges-and-configuration-address-space/m-p/653049#M15002 AArqu 2020-05-15T08:48:47Z https://community.intel.com/t5/Items-with-no-label/PCI-bridges-and-configuration-address-space/m-p/653050#M15003 <P>Could someoe shine some light on this?</P> Sat, 23 May 2020 14:40:38 GMT https://community.intel.com/t5/Items-with-no-label/PCI-bridges-and-configuration-address-space/m-p/653050#M15003 AArqu 2020-05-23T14:40:38Z