topic Re: vectorizing with a constant conditional in Intel® Fortran Compiler

vectorizing with a constant conditional

joe_krahn — Tue, 18 Apr 2006 22:34:28 GMT

I used to avoid conditionals inside of loops, but it seems that modern optimizers generally can move constant conditionals out of the loop, making two versions of the loop where needed. I started to think that manually creating two loops to avoid inner-loop conditionals was no longer necessary, but I am finding that such conditionals prevent Intel Fortran from vectorizing loops.

Am I incorrect in thinking that optimizers can avoid re-evaluating inner conditionals, or are the vectorized optimizations just not as robust? Or, maybe it actually depends on the conditional, and not vectorization; I haven't done a lot of testing. Is there documentation on what the optimizer can/cannot do for loops with conditionals?

Thanks!

Re: vectorizing with a constant conditional

Intel_C_Intel — Wed, 19 Apr 2006 00:30:41 GMT

Dear Joe,

Due to historical reasons, some but not all loop-oriented optimizations have been applied by the time the vectorizer runs. As a result, often one would see that only loops with simple loop invariant conditionals are vectorized using bit-masking, followed by invariant code hoisting on the vector instructions. Clearly, this is open for improvement and you are hopefully happy to hear that we are currently doing major rewrite of the vectorizer/threadizer to addresses this and related phase-ordering issues.

As for documentation, the Software Vectorization Handbook (http://www.intel.com/intelpress/sum_vmmx.htm) provides in in-depth presentation of Intels vectorization methodology, including conditional vectorization.

Hope this helps.

Aart Bik
http://www.aartbik.com/