topic Output of lpm_divide is x's when inputs are 0 in modelsim in FPGA Intellectual Property
https://community.intel.com/t5/FPGA-Intellectual-Property/Output-of-lpm-divide-is-x-s-when-inputs-are-0-in-modelsim/m-p/182558#M14666
<P>I am doing simulations in a design that uses the lpm_divide megafunction. I noticed that I am having issues since the output of lpm_divide is x's (for both outputs) when the inputs are 0. Is there any way to change the output to 0 without causing any additional latency?</P>Fri, 25 Jan 2013 06:23:38 GMTAltera_Forum2013-01-25T06:23:38ZOutput of lpm_divide is x's when inputs are 0 in modelsim
https://community.intel.com/t5/FPGA-Intellectual-Property/Output-of-lpm-divide-is-x-s-when-inputs-are-0-in-modelsim/m-p/182558#M14666
<P>I am doing simulations in a design that uses the lpm_divide megafunction. I noticed that I am having issues since the output of lpm_divide is x's (for both outputs) when the inputs are 0. Is there any way to change the output to 0 without causing any additional latency?</P>Fri, 25 Jan 2013 06:23:38 GMThttps://community.intel.com/t5/FPGA-Intellectual-Property/Output-of-lpm-divide-is-x-s-when-inputs-are-0-in-modelsim/m-p/182558#M14666Altera_Forum2013-01-25T06:23:38ZRe: Output of lpm_divide is x's when inputs are 0 in modelsim
https://community.intel.com/t5/FPGA-Intellectual-Property/Output-of-lpm-divide-is-x-s-when-inputs-are-0-in-modelsim/m-p/182559#M14667
<P>Although zero divide by zero is mathematically NAN (not-a-number), a parallel divider should give a defined '0'/'1' bit vector. </P><P></P> <P></P>I don't see a reason to expect an all '0' output. <P></P> <P></P>The MegaFunction user manual specifies 'x' output for divide by zero. I think, this means it's up to the synthesis tool optimization to make individual bit either '0' or '1'. The simulator is apparently reflecting this ambiguity, you should run a gate level simulation to see the actual output. Forcing zero output for divide by zero requires additional logic anyway.Fri, 25 Jan 2013 14:46:05 GMThttps://community.intel.com/t5/FPGA-Intellectual-Property/Output-of-lpm-divide-is-x-s-when-inputs-are-0-in-modelsim/m-p/182559#M14667Altera_Forum2013-01-25T14:46:05ZRe: Output of lpm_divide is x's when inputs are 0 in modelsim
https://community.intel.com/t5/FPGA-Intellectual-Property/Output-of-lpm-divide-is-x-s-when-inputs-are-0-in-modelsim/m-p/182560#M14668
<P>I can't test it with gate-level simulation so I have to use RTL. Since timing is not even checked in RTL, I guess that I could add that extra logic in since it won't affect anything until I actually compile the design.</P>Sat, 26 Jan 2013 01:25:39 GMThttps://community.intel.com/t5/FPGA-Intellectual-Property/Output-of-lpm-divide-is-x-s-when-inputs-are-0-in-modelsim/m-p/182560#M14668Altera_Forum2013-01-26T01:25:39Z