topic Re: FFT need help in FPGA Intellectual Property
https://community.intel.com/t5/FPGA-Intellectual-Property/FFT-need-help/m-p/80857#M6197
<P>Hello, </P><P></P> <P></P>Thanks for this document, but I have still problems :p <P></P> <P></P>For the clock it's ok, I understand what it is. But then ... <P></P>Reset_n : it's for reset the FFT before get a new signal ? <P></P> <P></P>I don't understand what are the sink_*** input (or output maybe). What is their utility ? <P></P> <P></P>And for the source, how I must link it to the FFT ? I think I have to use source_real and source_imag but I don't understand the difference between these input. <P></P> <P></P>The source_valid and source_ready, I think it's ok. <P></P> <P></P>So if someone can explain me what are the inputs I have to use to get my signal in the FFT, and the utility of sink_*** I/O, it will be very good :D <P></P> <P></P>Sorry if it's explain in the pdf, but I don't understand everything.Fri, 23 Apr 2010 14:38:46 GMTAltera_Forum2010-04-23T14:38:46ZFFT need help
https://community.intel.com/t5/FPGA-Intellectual-Property/FFT-need-help/m-p/80855#M6195
<P>Hello, </P><P></P> <P></P>I'm working on quartus for a project and I have to create an FFT block, but I never work on Quartus and I don't understand how I can link it. I just want to create a generator and an FFT, but I don't know how link them. <P></P> <P></P>Someone can explain me the input/output of FFT block ? <P></P> <P></P>Thanks <P></P> <P></P>PS: Sorry for my English, I'm french.Tue, 20 Apr 2010 20:55:38 GMThttps://community.intel.com/t5/FPGA-Intellectual-Property/FFT-need-help/m-p/80855#M6195Altera_Forum2010-04-20T20:55:38ZRe: FFT need help
https://community.intel.com/t5/FPGA-Intellectual-Property/FFT-need-help/m-p/80856#M6196
<P>Hello, </P><P></P> <P></P>You can find all the information about the FFT in the FFT Megacore Function User Guide (<A href="http://www.altera.com/literature/ug/ug_fft.pdf">http://www.altera.com/literature/ug/ug_fft.pdf</A>). Take a look on it, and come back if there are still things that are not clear. <P></P> <P></P>JérômeWed, 21 Apr 2010 15:25:48 GMThttps://community.intel.com/t5/FPGA-Intellectual-Property/FFT-need-help/m-p/80856#M6196Altera_Forum2010-04-21T15:25:48ZRe: FFT need help
https://community.intel.com/t5/FPGA-Intellectual-Property/FFT-need-help/m-p/80857#M6197
<P>Hello, </P><P></P> <P></P>Thanks for this document, but I have still problems :p <P></P> <P></P>For the clock it's ok, I understand what it is. But then ... <P></P>Reset_n : it's for reset the FFT before get a new signal ? <P></P> <P></P>I don't understand what are the sink_*** input (or output maybe). What is their utility ? <P></P> <P></P>And for the source, how I must link it to the FFT ? I think I have to use source_real and source_imag but I don't understand the difference between these input. <P></P> <P></P>The source_valid and source_ready, I think it's ok. <P></P> <P></P>So if someone can explain me what are the inputs I have to use to get my signal in the FFT, and the utility of sink_*** I/O, it will be very good :D <P></P> <P></P>Sorry if it's explain in the pdf, but I don't understand everything.Fri, 23 Apr 2010 14:38:46 GMThttps://community.intel.com/t5/FPGA-Intellectual-Property/FFT-need-help/m-p/80857#M6197Altera_Forum2010-04-23T14:38:46ZRe: FFT need help
https://community.intel.com/t5/FPGA-Intellectual-Property/FFT-need-help/m-p/80858#M6198
<P>For the reset, it is a classical reset signal, just set it to 0 at the start up of the system, and then 1. </P><P></P> <P></P>sink_real and sink_imag is your input signal. <P></P> <P></P>sink_valid is a kind of enable to tell to the FFT that there is signal at its input. <P></P>sink_sop/eop is to tell to the FFT when to begin and when to finish, thats corresponds to the begin of your signal and its end. (see Fig 3-4) <P></P> <P></P>sink_ready is set by the FFT to tell you if it can process data or not. It is not useful for streaming architecture (see Fig 3-3), but it is for the buffered ones (see Fig 3-11 and 3-14). <P></P> <P></P>And the source_* are the equivalence of these signals for the output.Mon, 26 Apr 2010 17:57:31 GMThttps://community.intel.com/t5/FPGA-Intellectual-Property/FFT-need-help/m-p/80858#M6198Altera_Forum2010-04-26T17:57:31Z