topic Re: DE2 Lab 7, Part 7 (VHDL) - Digital Logic in IntelĀ® FPGA University Program
https://community.intel.com/t5/Intel-FPGA-University-Program/DE2-Lab-7-Part-7-VHDL-Digital-Logic/m-p/56189#M858
<P>Dont use the keys as clocks. </P><P></P>You're asking for trouble. <P></P> <P></P>Clock the process with the system clock. You can make a falling edge detector by registering the key states, then you can do: <P></P> <P></P>if key(0) = '0' and key_old(0) = '1' then <P></P> <P></P>Clocking the process will also get you away from the incomplete sensitivity list you have at the moment.Wed, 25 Aug 2010 14:24:08 GMTAltera_Forum2010-08-25T14:24:08ZDE2 Lab 7, Part 7 (VHDL) - Digital Logic
https://community.intel.com/t5/Intel-FPGA-University-Program/DE2-Lab-7-Part-7-VHDL-Digital-Logic/m-p/56188#M857
<P>I just started learning VHDL and FPGA programing a couple of weeks ago and am currently working on Lab 7, Part 7 of the DE2 digital logic VHDL labs provided by Altera. </P><P></P> <P></P>In this lab you have to code two finite-state machines. One for a scrolling 'hello' and another to determine what speed it should scroll at, judging on the key button the user presses. <P></P> <P></P>I'm having trouble with the FSM that recognizes the speed. As it explains in the lab, if you press KEY(1) it increases in speed and if you press KEY(2) it decreases. I want to make this on the falling edge of each key press so that there is only one state change for each button press. <P></P> <P></P>Here is the code I have for the FSM. Obviously this isn't correct and won't compile but I'm just copying it to illustrate where I'm stuck: <P></P> <P></P><CODE> PROCESS (KEY(1), KEY(2))
BEGIN
CASE y2 IS
WHEN A =>
IF ((KEY(1)'event) AND (KEY(1) = '0')) THEN
y2 <= B;
ELSIF ((KEY(2)'event) AND (KEY(2) = '0')) THEN
y2 <= D;
END IF;
Stop <= 50000000;
WHEN B =>
IF ((KEY(1)'event) AND (KEY(1) = '0')) THEN
y2 <= C;
ELSIF ((KEY(2)'event) AND (KEY(2) = '0')) THEN
y2 <= A;
END IF;
Stop <= 25000000;
WHEN C =>
IF ((KEY(1)'event) AND (KEY(1) = '0')) THEN
y2 <= C;
ELSIF ((KEY(2)'event) AND (KEY(2) = '0')) THEN
y2 <= B;
END IF;
Stop <= 12500000;
WHEN D =>
IF ((KEY(1)'event) AND (KEY(1) = '0')) THEN
y2 <= A;
ELSIF ((KEY(2)'event) AND (KEY(2) = '0')) THEN
y2 <= E;
END IF;
Stop <= 100000000;
WHEN E =>
IF ((KEY(1)'event) AND (KEY(1) = '0')) THEN
y2 <= D;
ELSIF ((KEY(2)'event) AND (KEY(2) = '0')) THEN
y2 <= E;
END IF;
Stop <= 200000000;
END CASE;
END PROCESS;</CODE>For clarification, the variable 'Stop' tells my other FSM how many clock cycles it should go through before moving the letters left. <P></P> <P></P>Clearly the FSM has trouble with the two clocks (the key presses) for every state. What approach could I take to solve this problem? My previous FSM is clocked by a single clock but here I have to worry about two and the states depend on which one is pressed so I'm a little stuck with ideas. <P></P> <P></P>Just to point out, I could just use KEY(1) = '0' instead of making it depend on the falling edge but in that case it would immediately jump to the last state and I only want 1 state to change with 1 button press. Hopefully this all makes some sense :)Wed, 25 Aug 2010 11:27:02 GMThttps://community.intel.com/t5/Intel-FPGA-University-Program/DE2-Lab-7-Part-7-VHDL-Digital-Logic/m-p/56188#M857Altera_Forum2010-08-25T11:27:02ZRe: DE2 Lab 7, Part 7 (VHDL) - Digital Logic
https://community.intel.com/t5/Intel-FPGA-University-Program/DE2-Lab-7-Part-7-VHDL-Digital-Logic/m-p/56189#M858
<P>Dont use the keys as clocks. </P><P></P>You're asking for trouble. <P></P> <P></P>Clock the process with the system clock. You can make a falling edge detector by registering the key states, then you can do: <P></P> <P></P>if key(0) = '0' and key_old(0) = '1' then <P></P> <P></P>Clocking the process will also get you away from the incomplete sensitivity list you have at the moment.Wed, 25 Aug 2010 14:24:08 GMThttps://community.intel.com/t5/Intel-FPGA-University-Program/DE2-Lab-7-Part-7-VHDL-Digital-Logic/m-p/56189#M858Altera_Forum2010-08-25T14:24:08ZRe: DE2 Lab 7, Part 7 (VHDL) - Digital Logic
https://community.intel.com/t5/Intel-FPGA-University-Program/DE2-Lab-7-Part-7-VHDL-Digital-Logic/m-p/56190#M859
<P> </P><P></P> --- Quote Start --- <P></P>Dont use the keys as clocks. <P></P>You're asking for trouble. <P></P> <P></P>Clock the process with the system clock. You can make a falling edge detector by registering the key states, then you can do: <P></P> <P></P>if key(0) = '0' and key_old(0) = '1' then <P></P> <P></P>Clocking the process will also get you away from the incomplete sensitivity list you have at the moment. <P></P> --- Quote End --- <P></P> <P></P> <P></P>Thanks a lot for the advice, exactly what I was looking for. I implemented your method and it works great. Thanks.Thu, 26 Aug 2010 08:49:52 GMThttps://community.intel.com/t5/Intel-FPGA-University-Program/DE2-Lab-7-Part-7-VHDL-Digital-Logic/m-p/56190#M859Altera_Forum2010-08-26T08:49:52Z