topic Re: How to enable VGA support? in GPU Compute Software

How to enable VGA support?

OTS — Sat, 05 Aug 2023 11:09:34 GMT

Hello,
I'd like to enable VGA support on graphics circuits from Intel but fail to do so.

First I set up a display mode using a generation x graphics standard:

clock generator speed = 152,857,142 Hz
image refreshing rate = 65 Hz
x.input drawing area size = 1,920 pixels
y.input drawing area size = 1,200 lines

So far, this works.

Then I'd like to disable generation x support (if necessary) and enable VGA support:

# disable output connector
digital display port B control["digital display port B enable"] = false
# disable non-VGA plane
display A plane control["display plane A enable"] = false
# disable timing control via generation x and enable timing control via VGA
VGA display plane control["VGA display disable"] = false
VGA display plane control["VGA centering enable"] = 00|b
# disable image pipeline
pipe A configuration["pipe A enable"] = false
wait until pipe A configuration["pipe state"] == false
# disable clock generator (digital phase-locked loop)
DPLL A control["DPLL A VCO enable"] = false
DPLL A control["DPLL A external clock buffer enable"] = false
# disable clock generator control via generation x and enable clock generator control via VGA
DPLL A control["VGA mode disable"] = false
# enable clock generator
DPLL A control["DPLL A VCO enable"] = true
DPLL A control["DPLL A external clock buffer enable"] = true
# enable image pipeline
pipe A configuration["pipe A enable"] = true
wait until pipe A configuration["pipe state"] == true
# enable output connector
digital display port B control["digital display port B enable"] = true

Now I would expect, that the clock generator speed changes to one of the VGA clock generator speeds:

12,587,500|d Hz (25 MHz / 2)
14,161,000|d Hz (28 MHz / 2)
25,175,000|d Hz
28,322,000|d Hz

But it doesn't. My oscilloscope says, that the speed remains at 153,374,233 Hz.

Does someone know the correct sequence to activate VGA support?

Thank you.

Re:How to enable VGA support?

Hugo_Intel — Mon, 07 Aug 2023 22:31:14 GMT

Hello OTS

Thank you for posting on the Intel️® communities.

We will move your question to the correct sub-forum, the team in charge will get back to you soon.

Best regards,

Hugo O.

Intel Customer Support Technician

Re: How to enable VGA support?

OTS — Tue, 22 Aug 2023 00:22:12 GMT

I am still interested, if anyone cares.

Re: How to enable VGA support?

OTS — Fri, 09 Aug 2024 12:37:57 GMT

I think I found a work around and I am finally able to use VGA, well at least more or less. Here is my solution:

The Valleyview graphics circuit has

a register called "DPLL A control register" and
a register called "DPLL B control register".

Both registers have a field called "VGA mode disable" (bit 2^28). Normally one would set the value in this field to 0 to activate the option, that the clock generator speed depends on the value set in the VGA configuration register. However, the graphic circuit ignores this value and never uses the value from the VGA configuration register. So switching between 25.175 MHz and 28.322 MHz via VGA is not possible. The graphics circuit always reads the speed from the DPLL configuration registers.

The next problem is, that the DPLL doesn't seem to have the following registers:

"VGA 0 divisor",
"VGA 1 divisor" and
"VGA post divisor values"

These missing registers are normally used to define a set of values which should be used instead of the DPLL configuration registers. So instead of reading from the DPLL configuration registers the graphics circuit normally

either reads "VGA 0 divisor" + "VGA post divisor values" to generate 25.175 MHz
or it reads "VGA 1 divisor" + "VGA post divisor values" to generate 28.322 MHz.

Since these registers seem to be missing this is another reason why switching between 25.175 MHz and 28.322 MHz via VGA is not possible.

To solve this problem the only solution I have found so far is to set the clock generator speed not by using the graphics standard "video graphics array" but rather the graphics standard "generation 7.0 low cost". With other words: Writing to the DPLL configuration registers via the side band interface. The rest of the display mode can be set with the VGA-configuration-registers. So 16 color modes and below become possible with this Frankenstein-configuration.

It's a bug work-around but I haven't found anything better so far.