https://community.intel.com/t5/Graphics/Mobile-Chipset-QM57-PCIe-communication/m-p/365423#M25596 <P>Does the QM57 chipset support peer to peer PCIe communication (two PCIe end points talking to each other without going through the processor)?</P><P>I have looked through all the documentation I can find, and I haven't been able to find it explicitly stated anywhere.</P><P></P><P>Is it typical for a general purpose PCH to support peer to peer PCIe communcation?</P> Mon, 28 Mar 2011 17:12:26 GMT idata 2011-03-28T17:12:26Z https://community.intel.com/t5/Graphics/Mobile-Chipset-QM57-PCIe-communication/m-p/365423#M25596 <P>Does the QM57 chipset support peer to peer PCIe communication (two PCIe end points talking to each other without going through the processor)?</P><P>I have looked through all the documentation I can find, and I haven't been able to find it explicitly stated anywhere.</P><P></P><P>Is it typical for a general purpose PCH to support peer to peer PCIe communcation?</P> Mon, 28 Mar 2011 17:12:26 GMT https://community.intel.com/t5/Graphics/Mobile-Chipset-QM57-PCIe-communication/m-p/365423#M25596 idata 2011-03-28T17:12:26Z https://community.intel.com/t5/Graphics/Mobile-Chipset-QM57-PCIe-communication/m-p/365424#M25597 <P>Still trying to find this information. </P> Thu, 07 Apr 2011 16:36:23 GMT https://community.intel.com/t5/Graphics/Mobile-Chipset-QM57-PCIe-communication/m-p/365424#M25597 idata 2011-04-07T16:36:23Z