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    <title>topic Re: Realtionship between EU and shader? in Graphics</title>
    <link>https://community.intel.com/t5/Graphics/Realtionship-between-EU-and-shader/m-p/382546#M28341</link>
    <description>&lt;P&gt;Hello SydneyPhil,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;At this point the information is not handy for me but let me research and I will be right back with you as soon as possible.&lt;/P&gt;</description>
    <pubDate>Fri, 26 Jul 2013 20:46:56 GMT</pubDate>
    <dc:creator>Kevin_M_Intel</dc:creator>
    <dc:date>2013-07-26T20:46:56Z</dc:date>
    <item>
      <title>Realtionship between EU and shader?</title>
      <link>https://community.intel.com/t5/Graphics/Realtionship-between-EU-and-shader/m-p/382545#M28340</link>
      <description>&lt;P&gt;I'm coming from a CUDA background, and want to wrap my mind around the different graphics terminology in Intel chips. On NVidia harware, groups of threads (each in a core) are scheduled to run on one of a small number of streaming multiprocessors. Is there a similar relationship between EU (=SM) and shader (=core)?&lt;/P&gt;</description>
      <pubDate>Fri, 21 Jun 2013 04:44:07 GMT</pubDate>
      <guid>https://community.intel.com/t5/Graphics/Realtionship-between-EU-and-shader/m-p/382545#M28340</guid>
      <dc:creator>PCox</dc:creator>
      <dc:date>2013-06-21T04:44:07Z</dc:date>
    </item>
    <item>
      <title>Re: Realtionship between EU and shader?</title>
      <link>https://community.intel.com/t5/Graphics/Realtionship-between-EU-and-shader/m-p/382546#M28341</link>
      <description>&lt;P&gt;Hello SydneyPhil,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;At this point the information is not handy for me but let me research and I will be right back with you as soon as possible.&lt;/P&gt;</description>
      <pubDate>Fri, 26 Jul 2013 20:46:56 GMT</pubDate>
      <guid>https://community.intel.com/t5/Graphics/Realtionship-between-EU-and-shader/m-p/382546#M28341</guid>
      <dc:creator>Kevin_M_Intel</dc:creator>
      <dc:date>2013-07-26T20:46:56Z</dc:date>
    </item>
    <item>
      <title>Re: Realtionship between EU and shader?</title>
      <link>https://community.intel.com/t5/Graphics/Realtionship-between-EU-and-shader/m-p/382547#M28342</link>
      <description>&lt;P&gt;You can refer to this URL for information:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="https://01.org/linuxgraphics/sites/default/files/documentation/ivb_ihd_os_vol1_part1.pdf"&gt;https://01.org/linuxgraphics/sites/default/files/documentation/ivb_ihd_os_vol1_part1.pdf&lt;/A&gt; &lt;A href="https://01.org/linuxgraphics/sites/default/files/documentation/ivb_ihd_os_vol1_part1.pdf"&gt;https://01.org/linuxgraphics/sites/default/files/documentation/ivb_ihd_os_vol1_part1.pdf&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Check on page 15 and page 18, they contain information on the EU's.  Basically an EU is a sub-section of the processor that splits process information using an even further sub-section of "threads".  The listed information on page 18 states that an Ivy Bridge processor can have 16 EU's on it, each with 8 threads of their own for processing/sub-processing.&lt;/P&gt;</description>
      <pubDate>Wed, 07 Aug 2013 16:39:54 GMT</pubDate>
      <guid>https://community.intel.com/t5/Graphics/Realtionship-between-EU-and-shader/m-p/382547#M28342</guid>
      <dc:creator>DArce</dc:creator>
      <dc:date>2013-08-07T16:39:54Z</dc:date>
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