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    <title>topic Re: EM2120L01QI SYNC pin's capacitance in Graphics</title>
    <link>https://community.intel.com/t5/Graphics/EM2120L01QI-SYNC-pin-s-capacitance/m-p/646812#M76437</link>
    <description>&lt;P&gt;close it. 10pF around.&lt;/P&gt;&lt;P&gt;and  EM2120 sync function is OFF by default, need to be Enabled by I2C bus......&lt;/P&gt;</description>
    <pubDate>Sat, 08 Jun 2019 19:10:12 GMT</pubDate>
    <dc:creator>xytech</dc:creator>
    <dc:date>2019-06-08T19:10:12Z</dc:date>
    <item>
      <title>EM2120L01QI SYNC pin's capacitance</title>
      <link>https://community.intel.com/t5/Graphics/EM2120L01QI-SYNC-pin-s-capacitance/m-p/646811#M76436</link>
      <description>&lt;P&gt;Hi, we use FPGA to generate ONLY ONE external sync clock singal to feed all 15 pcs of EM2120 sync pins on our big power system, connected in daisy-chain topology. &lt;/P&gt;&lt;P&gt;&lt;B&gt;Could you pls tell the SYNC pin's capacitance? &lt;/B&gt;&lt;/P&gt;&lt;P&gt;As the output current strength of FPGA pin is about only 4~8mA， we are not should whether it is &lt;B&gt;enough&lt;/B&gt; to drive so many sync pins. We need to know the total capacitive load to decide whether a buffer IC should be inserted.&lt;/P&gt;</description>
      <pubDate>Thu, 06 Jun 2019 18:53:36 GMT</pubDate>
      <guid>https://community.intel.com/t5/Graphics/EM2120L01QI-SYNC-pin-s-capacitance/m-p/646811#M76436</guid>
      <dc:creator>xytech</dc:creator>
      <dc:date>2019-06-06T18:53:36Z</dc:date>
    </item>
    <item>
      <title>Re: EM2120L01QI SYNC pin's capacitance</title>
      <link>https://community.intel.com/t5/Graphics/EM2120L01QI-SYNC-pin-s-capacitance/m-p/646812#M76437</link>
      <description>&lt;P&gt;close it. 10pF around.&lt;/P&gt;&lt;P&gt;and  EM2120 sync function is OFF by default, need to be Enabled by I2C bus......&lt;/P&gt;</description>
      <pubDate>Sat, 08 Jun 2019 19:10:12 GMT</pubDate>
      <guid>https://community.intel.com/t5/Graphics/EM2120L01QI-SYNC-pin-s-capacitance/m-p/646812#M76437</guid>
      <dc:creator>xytech</dc:creator>
      <dc:date>2019-06-08T19:10:12Z</dc:date>
    </item>
    <item>
      <title>Re: EM2120L01QI SYNC pin's capacitance</title>
      <link>https://community.intel.com/t5/Graphics/EM2120L01QI-SYNC-pin-s-capacitance/m-p/646813#M76438</link>
      <description>&lt;P&gt;Hello Yi Xiao,&lt;/P&gt;&lt;P&gt;You are correct, and thanks for answering the case.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;mostafa&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 21 Jun 2019 14:04:58 GMT</pubDate>
      <guid>https://community.intel.com/t5/Graphics/EM2120L01QI-SYNC-pin-s-capacitance/m-p/646813#M76438</guid>
      <dc:creator>Mostafa_Intel_AE</dc:creator>
      <dc:date>2019-06-21T14:04:58Z</dc:date>
    </item>
    <item>
      <title>Re: EM2120L01QI SYNC pin's capacitance</title>
      <link>https://community.intel.com/t5/Graphics/EM2120L01QI-SYNC-pin-s-capacitance/m-p/646814#M76439</link>
      <description>&lt;P&gt;Hi, mostafa, &lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;coud you please help look on this question? Thanks.&lt;/P&gt;&lt;P&gt;&lt;A href="https://forums.intel.com/s/question/0D50P00004MxMGQSA3/allowed-maximum-mechanical-pressure-when-mounting-heatsink-on-top-of-em2120l01qi"&gt;https://forums.intel.com/s/question/0D50P00004MxMGQSA3/allowed-maximum-mechanical-pressure-when-mounting-heatsink-on-top-of-em2120l01qi&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 27 Jun 2019 07:35:05 GMT</pubDate>
      <guid>https://community.intel.com/t5/Graphics/EM2120L01QI-SYNC-pin-s-capacitance/m-p/646814#M76439</guid>
      <dc:creator>xytech</dc:creator>
      <dc:date>2019-06-27T07:35:05Z</dc:date>
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