<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic IPP and parallel nested scenarios with affinity masks in Intel® Integrated Performance Primitives</title>
    <link>https://community.intel.com/t5/Intel-Integrated-Performance/IPP-and-parallel-nested-scenarios-with-affinity-masks/m-p/908909#M13882</link>
    <description>Hi,&lt;BR /&gt;&lt;BR /&gt;Are there any documention/sample available, which describe parallel nested scenarios with IPP function calls where P1 (Parallel Task 1) and P2 (Parallel Task 2) using complement affinity masks (e.g. 1-4 cores are assigned to P1, while 5-7 cores are assigned to P2, and both threads use the setNumThreads(4 or 3) calls?&lt;BR /&gt;&lt;BR /&gt;Is such a CPU resource allocation scheme possible with IPP?&lt;BR /&gt;&lt;BR /&gt;Thanks in advance,&lt;BR /&gt;Tamas</description>
    <pubDate>Mon, 27 Jul 2009 14:04:35 GMT</pubDate>
    <dc:creator>mailtamas-nagy_net</dc:creator>
    <dc:date>2009-07-27T14:04:35Z</dc:date>
    <item>
      <title>IPP and parallel nested scenarios with affinity masks</title>
      <link>https://community.intel.com/t5/Intel-Integrated-Performance/IPP-and-parallel-nested-scenarios-with-affinity-masks/m-p/908909#M13882</link>
      <description>Hi,&lt;BR /&gt;&lt;BR /&gt;Are there any documention/sample available, which describe parallel nested scenarios with IPP function calls where P1 (Parallel Task 1) and P2 (Parallel Task 2) using complement affinity masks (e.g. 1-4 cores are assigned to P1, while 5-7 cores are assigned to P2, and both threads use the setNumThreads(4 or 3) calls?&lt;BR /&gt;&lt;BR /&gt;Is such a CPU resource allocation scheme possible with IPP?&lt;BR /&gt;&lt;BR /&gt;Thanks in advance,&lt;BR /&gt;Tamas</description>
      <pubDate>Mon, 27 Jul 2009 14:04:35 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Integrated-Performance/IPP-and-parallel-nested-scenarios-with-affinity-masks/m-p/908909#M13882</guid>
      <dc:creator>mailtamas-nagy_net</dc:creator>
      <dc:date>2009-07-27T14:04:35Z</dc:date>
    </item>
    <item>
      <title>Re: IPP and parallel nested scenarios with affinity masks</title>
      <link>https://community.intel.com/t5/Intel-Integrated-Performance/IPP-and-parallel-nested-scenarios-with-affinity-masks/m-p/908910#M13883</link>
      <description>&lt;DIV style="margin:0px;"&gt;&lt;/DIV&gt;
&lt;BR /&gt;It is not possible to do in the IPP 6.1. We are working on additional API for IPP internal threads affinity setting for the next version of IPP&lt;BR /&gt;&lt;BR /&gt;Regards,&lt;BR /&gt; Vladimir</description>
      <pubDate>Tue, 28 Jul 2009 13:57:26 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Integrated-Performance/IPP-and-parallel-nested-scenarios-with-affinity-masks/m-p/908910#M13883</guid>
      <dc:creator>Vladimir_Dudnik</dc:creator>
      <dc:date>2009-07-28T13:57:26Z</dc:date>
    </item>
  </channel>
</rss>

