https://community.intel.com/t5/Intel-Integrated-Performance/Why-is-it-so/m-p/940861#M17643 <DIV>int stepMCU2,stepMCU;</DIV> <DIV>Ipp16s* pDstMCU[3];</DIV> <DIV>pDstMCU[0]=ippiMalloc_16s_C1(16,8,&amp;stepMCU2);</DIV> <DIV> <DIV>pDstMCU[1]=ippiMalloc_16s_C1(8,8,&amp;stepMCU);</DIV> <DIV></DIV> <DIV>Why does 'stepMCU2' and 'stepMCU' both become 32?</DIV> <DIV>I think 'stepMCU' should be 16(8*2=16).</DIV></DIV> Tue, 14 Mar 2006 09:28:05 GMT tkx007 2006-03-14T09:28:05Z https://community.intel.com/t5/Intel-Integrated-Performance/Why-is-it-so/m-p/940861#M17643 <DIV>int stepMCU2,stepMCU;</DIV> <DIV>Ipp16s* pDstMCU[3];</DIV> <DIV>pDstMCU[0]=ippiMalloc_16s_C1(16,8,&amp;stepMCU2);</DIV> <DIV> <DIV>pDstMCU[1]=ippiMalloc_16s_C1(8,8,&amp;stepMCU);</DIV> <DIV></DIV> <DIV>Why does 'stepMCU2' and 'stepMCU' both become 32?</DIV> <DIV>I think 'stepMCU' should be 16(8*2=16).</DIV></DIV> Tue, 14 Mar 2006 09:28:05 GMT https://community.intel.com/t5/Intel-Integrated-Performance/Why-is-it-so/m-p/940861#M17643 tkx007 2006-03-14T09:28:05Z https://community.intel.com/t5/Intel-Integrated-Performance/Why-is-it-so/m-p/940862#M17644 <P>According IPP manual, ippMalloc use alignment to 32 byte boundary</P> <P>Vladimir</P> <DIV></DIV> Tue, 14 Mar 2006 09:35:32 GMT https://community.intel.com/t5/Intel-Integrated-Performance/Why-is-it-so/m-p/940862#M17644 Vladimir_Dudnik 2006-03-14T09:35:32Z https://community.intel.com/t5/Intel-Integrated-Performance/Why-is-it-so/m-p/940863#M17645 <DIV>I see,thanks!!</DIV> Tue, 14 Mar 2006 10:18:10 GMT https://community.intel.com/t5/Intel-Integrated-Performance/Why-is-it-so/m-p/940863#M17645 tkx007 2006-03-14T10:18:10Z