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    <title>topic IPP memory functions in Intel® Integrated Performance Primitives</title>
    <link>https://community.intel.com/t5/Intel-Integrated-Performance/IPP-memory-functions/m-p/949830#M18526</link>
    <description>&lt;DIV&gt;Can you give some details about IPP dynamic memory allocation functions? Do you have your own optimized heap implementation, or it is just a wrapper for existing Operating System's malloc() that ensures proper alignment?&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;It's well known that, for example, default Visual C++ heap manager is not any good in multithreaded environment, especially on SMP systems.&lt;/DIV&gt;
&lt;DIV&gt;Looks at the following benchmarks:&lt;BR /&gt;&lt;A href="http://www.microquill.com/smartheapsmp/index.html" target="_blank"&gt;http://www.microquill.com/smartheapsmp/index.html&lt;/A&gt;&lt;BR /&gt;&lt;A href="http://www.winheap.com/winheap_info/benchmarks.php" target="_blank"&gt;http://www.winheap.com/winheap_info/benchmarks.php&lt;/A&gt;&lt;/DIV&gt;
&lt;DIV&gt;It would be great if IPP provided decent heap manager of its own.&lt;/DIV&gt;
&lt;DIV&gt;You could base it on one of the free libraries (not sure on license terms) such as:&lt;BR /&gt;&lt;A href="http://www.cs.umass.edu/~emery/hoard/" target="_blank"&gt;http://www.cs.umass.edu/~emery/hoard/&lt;/A&gt;&lt;BR /&gt;&lt;A href="http://gee.cs.oswego.edu/dl/html/malloc.html" target="_blank"&gt;http://gee.cs.oswego.edu/dl/html/malloc.html&lt;/A&gt;&lt;BR /&gt;And make it configurable so that the IPP users could select the best heap implementation for their application.&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;</description>
    <pubDate>Wed, 07 Jul 2004 23:24:17 GMT</pubDate>
    <dc:creator>zxs</dc:creator>
    <dc:date>2004-07-07T23:24:17Z</dc:date>
    <item>
      <title>IPP memory functions</title>
      <link>https://community.intel.com/t5/Intel-Integrated-Performance/IPP-memory-functions/m-p/949830#M18526</link>
      <description>&lt;DIV&gt;Can you give some details about IPP dynamic memory allocation functions? Do you have your own optimized heap implementation, or it is just a wrapper for existing Operating System's malloc() that ensures proper alignment?&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;It's well known that, for example, default Visual C++ heap manager is not any good in multithreaded environment, especially on SMP systems.&lt;/DIV&gt;
&lt;DIV&gt;Looks at the following benchmarks:&lt;BR /&gt;&lt;A href="http://www.microquill.com/smartheapsmp/index.html" target="_blank"&gt;http://www.microquill.com/smartheapsmp/index.html&lt;/A&gt;&lt;BR /&gt;&lt;A href="http://www.winheap.com/winheap_info/benchmarks.php" target="_blank"&gt;http://www.winheap.com/winheap_info/benchmarks.php&lt;/A&gt;&lt;/DIV&gt;
&lt;DIV&gt;It would be great if IPP provided decent heap manager of its own.&lt;/DIV&gt;
&lt;DIV&gt;You could base it on one of the free libraries (not sure on license terms) such as:&lt;BR /&gt;&lt;A href="http://www.cs.umass.edu/~emery/hoard/" target="_blank"&gt;http://www.cs.umass.edu/~emery/hoard/&lt;/A&gt;&lt;BR /&gt;&lt;A href="http://gee.cs.oswego.edu/dl/html/malloc.html" target="_blank"&gt;http://gee.cs.oswego.edu/dl/html/malloc.html&lt;/A&gt;&lt;BR /&gt;And make it configurable so that the IPP users could select the best heap implementation for their application.&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;</description>
      <pubDate>Wed, 07 Jul 2004 23:24:17 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Integrated-Performance/IPP-memory-functions/m-p/949830#M18526</guid>
      <dc:creator>zxs</dc:creator>
      <dc:date>2004-07-07T23:24:17Z</dc:date>
    </item>
    <item>
      <title>Re: IPP memory functions</title>
      <link>https://community.intel.com/t5/Intel-Integrated-Performance/IPP-memory-functions/m-p/949831#M18527</link>
      <description>Some more&lt;BR /&gt;&lt;BR /&gt;Commercial:&lt;BR /&gt;&lt;A href="http://www.newcodeinc.com" target="_blank"&gt;http://www.newcodeinc.com&lt;/A&gt;&lt;BR /&gt;&lt;A href="http://www.leapheap.com" target="_blank"&gt;http://www.leapheap.com&lt;/A&gt;&lt;BR /&gt;&lt;BR /&gt;MSDN sample:&lt;BR /&gt;&lt;A href="http://tinyurl.com/25apl" target="_blank"&gt;http://tinyurl.com/25apl&lt;/A&gt;</description>
      <pubDate>Fri, 09 Jul 2004 23:17:51 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Integrated-Performance/IPP-memory-functions/m-p/949831#M18527</guid>
      <dc:creator>overspawn</dc:creator>
      <dc:date>2004-07-09T23:17:51Z</dc:date>
    </item>
    <item>
      <title>Re: IPP memory functions</title>
      <link>https://community.intel.com/t5/Intel-Integrated-Performance/IPP-memory-functions/m-p/949832#M18528</link>
      <description>&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;Some more food for thought:&lt;/DIV&gt;
&lt;DIV&gt;
&lt;DIV&gt;Other commercial libraries:&lt;/DIV&gt;
&lt;DIV&gt;&lt;A href="http://www.newcodeinc.com/" target="_top"&gt;http://www.newcodeinc.com&lt;/A&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;A href="http://www.leapheap.com/" target="_blank"&gt;http://www.leapheap.com/&lt;/A&gt;&lt;/DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;MSDN sample (MPHeap)&lt;/DIV&gt;
&lt;DIV&gt;&lt;A href="http://tinyurl.com/25apl" target="_blank"&gt;http://tinyurl.com/25apl&lt;/A&gt;&lt;/DIV&gt;</description>
      <pubDate>Fri, 09 Jul 2004 23:25:47 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Integrated-Performance/IPP-memory-functions/m-p/949832#M18528</guid>
      <dc:creator>zxs</dc:creator>
      <dc:date>2004-07-09T23:25:47Z</dc:date>
    </item>
    <item>
      <title>Re: IPP memory functions</title>
      <link>https://community.intel.com/t5/Intel-Integrated-Performance/IPP-memory-functions/m-p/949833#M18529</link>
      <description>&lt;DIV&gt;Hi,&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;currently we have just wrappers for C run time malloc/free, with adding allocation of aligned memory blocks. Thank you for information and suggestion, we will consider that.&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;Regards,&lt;/DIV&gt;
&lt;DIV&gt; Vladimir&lt;/DIV&gt;</description>
      <pubDate>Sun, 18 Jul 2004 21:18:31 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Integrated-Performance/IPP-memory-functions/m-p/949833#M18529</guid>
      <dc:creator>Vladimir_Dudnik</dc:creator>
      <dc:date>2004-07-18T21:18:31Z</dc:date>
    </item>
    <item>
      <title>Re: IPP memory functions</title>
      <link>https://community.intel.com/t5/Intel-Integrated-Performance/IPP-memory-functions/m-p/949834#M18530</link>
      <description>&lt;DIV&gt;One more link for completeness&lt;/DIV&gt;
&lt;DIV&gt;Cherry Stone Software ESA:&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;A href="http://www.cherrystonesoftware.com/" target="_blank"&gt;http://www.cherrystonesoftware.com/&lt;/A&gt;&lt;/DIV&gt;</description>
      <pubDate>Tue, 20 Jul 2004 22:02:22 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Integrated-Performance/IPP-memory-functions/m-p/949834#M18530</guid>
      <dc:creator>zxs</dc:creator>
      <dc:date>2004-07-20T22:02:22Z</dc:date>
    </item>
    <item>
      <title>Re: IPP memory functions</title>
      <link>https://community.intel.com/t5/Intel-Integrated-Performance/IPP-memory-functions/m-p/949835#M18531</link>
      <description>&lt;DIV&gt;Thank you again:)&lt;/DIV&gt;</description>
      <pubDate>Thu, 22 Jul 2004 02:33:30 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Integrated-Performance/IPP-memory-functions/m-p/949835#M18531</guid>
      <dc:creator>Vladimir_Dudnik</dc:creator>
      <dc:date>2004-07-22T02:33:30Z</dc:date>
    </item>
    <item>
      <title>Re: IPP memory functions</title>
      <link>https://community.intel.com/t5/Intel-Integrated-Performance/IPP-memory-functions/m-p/949836#M18532</link>
      <description>&lt;DIV&gt;I request thatyou also consider including a memory pooling policy in addition or as an adjunt to a more optimal allocation approach. Memory poolingis a requirement when doing continuousimage processing on video.&lt;/DIV&gt;

&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;

&lt;DIV&gt;Thanks,&lt;/DIV&gt;

&lt;DIV&gt;Phil&lt;/DIV&gt;</description>
      <pubDate>Thu, 22 Jul 2004 20:43:00 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Integrated-Performance/IPP-memory-functions/m-p/949836#M18532</guid>
      <dc:creator>Deleted_U_Intel</dc:creator>
      <dc:date>2004-07-22T20:43:00Z</dc:date>
    </item>
    <item>
      <title>Re: IPP memory functions</title>
      <link>https://community.intel.com/t5/Intel-Integrated-Performance/IPP-memory-functions/m-p/949837#M18533</link>
      <description>&lt;DIV&gt;Hi, what do you mean under pooling of memory?&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;Vladimir&lt;/DIV&gt;</description>
      <pubDate>Fri, 23 Jul 2004 22:54:17 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Integrated-Performance/IPP-memory-functions/m-p/949837#M18533</guid>
      <dc:creator>Vladimir_Dudnik</dc:creator>
      <dc:date>2004-07-23T22:54:17Z</dc:date>
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