https://community.intel.com/t5/Intel-Integrated-Performance/endian-for-ippsEncode-G726-16s8u/m-p/959613#M19541 Hi,<BR /><BR />As far as I know, there are 2 versions of G726 definitions from ITU and IETF. The one from IETF is little endian and ITU is big endian in terms of the packing of codeword.<BR /><BR />Is this function ippsEncode_G726_16s8u has any assumption about this? The sample g726 codec seems to be little endian.<BR /><BR />thanks,<BR />guoweis Fri, 02 Dec 2005 06:03:47 GMT gwshieh 2005-12-02T06:03:47Z https://community.intel.com/t5/Intel-Integrated-Performance/endian-for-ippsEncode-G726-16s8u/m-p/959613#M19541 Hi,<BR /><BR />As far as I know, there are 2 versions of G726 definitions from ITU and IETF. The one from IETF is little endian and ITU is big endian in terms of the packing of codeword.<BR /><BR />Is this function ippsEncode_G726_16s8u has any assumption about this? The sample g726 codec seems to be little endian.<BR /><BR />thanks,<BR />guoweis Fri, 02 Dec 2005 06:03:47 GMT https://community.intel.com/t5/Intel-Integrated-Performance/endian-for-ippsEncode-G726-16s8u/m-p/959613#M19541 gwshieh 2005-12-02T06:03:47Z https://community.intel.com/t5/Intel-Integrated-Performance/endian-for-ippsEncode-G726-16s8u/m-p/959614#M19542 <DIV>Hi,</DIV> <DIV>Function ippsEncode_G726_16s8u produces codewords in separete bytes. For example for32 kbp mode, size of one codeword -4 bits, so only4 bits in each byte are valid. You can pack it as you would like to have. G726 sample inIPP 5.0 is done according RFC 3551.</DIV> <DIV>Igor S. Belyakov</DIV> Mon, 05 Dec 2005 15:04:12 GMT https://community.intel.com/t5/Intel-Integrated-Performance/endian-for-ippsEncode-G726-16s8u/m-p/959614#M19542 Igor_B_Intel1 2005-12-05T15:04:12Z