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    <title>topic Processor Pipeline in Intel® Integrated Performance Primitives</title>
    <link>https://community.intel.com/t5/Intel-Integrated-Performance/Processor-Pipeline/m-p/966553#M20214</link>
    <description>Hi!&lt;BR /&gt;&lt;BR /&gt;I have a doubt.&lt;BR /&gt;if I have this code:&lt;BR /&gt;&lt;BR /&gt;b/=5;&lt;BR /&gt;a+=10;&lt;BR /&gt;b*=5;&lt;BR /&gt;a*=30;&lt;BR /&gt;&lt;BR /&gt;How the processor will execute this code?  &lt;BR /&gt;  &lt;BR /&gt;The add is more fast than the division, then the second command will finish before of the first. The processor will execute the fourth command or it will wait until that the second command was finished? It will execute of the program order or in another order?&lt;BR /&gt;&lt;BR /&gt;Thanks&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;[]'s&lt;BR /&gt;&lt;BR /&gt;Rhapsodyv</description>
    <pubDate>Fri, 19 Mar 2004 12:17:23 GMT</pubDate>
    <dc:creator>rhapsodyv</dc:creator>
    <dc:date>2004-03-19T12:17:23Z</dc:date>
    <item>
      <title>Processor Pipeline</title>
      <link>https://community.intel.com/t5/Intel-Integrated-Performance/Processor-Pipeline/m-p/966553#M20214</link>
      <description>Hi!&lt;BR /&gt;&lt;BR /&gt;I have a doubt.&lt;BR /&gt;if I have this code:&lt;BR /&gt;&lt;BR /&gt;b/=5;&lt;BR /&gt;a+=10;&lt;BR /&gt;b*=5;&lt;BR /&gt;a*=30;&lt;BR /&gt;&lt;BR /&gt;How the processor will execute this code?  &lt;BR /&gt;  &lt;BR /&gt;The add is more fast than the division, then the second command will finish before of the first. The processor will execute the fourth command or it will wait until that the second command was finished? It will execute of the program order or in another order?&lt;BR /&gt;&lt;BR /&gt;Thanks&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;[]'s&lt;BR /&gt;&lt;BR /&gt;Rhapsodyv</description>
      <pubDate>Fri, 19 Mar 2004 12:17:23 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Integrated-Performance/Processor-Pipeline/m-p/966553#M20214</guid>
      <dc:creator>rhapsodyv</dc:creator>
      <dc:date>2004-03-19T12:17:23Z</dc:date>
    </item>
    <item>
      <title>Re: Processor Pipeline</title>
      <link>https://community.intel.com/t5/Intel-Integrated-Performance/Processor-Pipeline/m-p/966554#M20215</link>
      <description>&lt;DIV&gt;Dear Customer,&lt;BR /&gt;I am not clear if this question is related to Intel IPP forum, could you please give us some more details so we can better understand about this and try to find a right resource to answer your questions.&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;Thanks,&lt;BR /&gt;Ying &lt;/DIV&gt;
&lt;DIV&gt;Intel IPP Support&lt;/DIV&gt;</description>
      <pubDate>Sat, 20 Mar 2004 05:03:23 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Integrated-Performance/Processor-Pipeline/m-p/966554#M20215</guid>
      <dc:creator>Ying_S_Intel</dc:creator>
      <dc:date>2004-03-20T05:03:23Z</dc:date>
    </item>
    <item>
      <title>Re: Processor Pipeline</title>
      <link>https://community.intel.com/t5/Intel-Integrated-Performance/Processor-Pipeline/m-p/966555#M20216</link>
      <description>&lt;P&gt;You know, the modern processors are able to execute instructions out of order, but theyoutputtheresult of instructions in order they are written in the programm. So, if there is no data dependency between adjacent instructions they will be executed in parallel, but if any dependency, of course the next instruction will wait for the result from previous one.&lt;/P&gt;
&lt;P&gt;Regards,&lt;BR /&gt; Vladimir&lt;/P&gt;
&lt;DIV&gt;&lt;/DIV&gt;</description>
      <pubDate>Wed, 24 Mar 2004 23:16:05 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Integrated-Performance/Processor-Pipeline/m-p/966555#M20216</guid>
      <dc:creator>Intel_C_Intel</dc:creator>
      <dc:date>2004-03-24T23:16:05Z</dc:date>
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