https://community.intel.com/t5/Intel-Integrated-Performance/FIR-LMS/m-p/970228#M20516 <DIV>Dear Customer,<BR />Could you please provide us more details on this report for the failure on calling FIRLMS functions by submitting an issue via Intel Premier Support at <A href="https://premier.intel.com" target="_blank">https://premier.intel.com</A>? Also it would be helpful to supply your test case that can replicate this problem, and our support staff will look into this problem.</DIV> <DIV></DIV> <DIV>Thanks,<BR />Ying <BR />Intel IPP</DIV> Wed, 18 Feb 2004 11:36:43 GMT Ying_S_Intel 2004-02-18T11:36:43Z https://community.intel.com/t5/Intel-Integrated-Performance/FIR-LMS/m-p/970227#M20515 <DIV></DIV> <DIV>I have a problem with working with FIR LMS.</DIV> <DIV>The program works well with tap length &lt; 32, however once i set it to 32, the result of the tap returns -1.#IND0 in the array.</DIV> <DIV></DIV> <DIV>FIR LMS fails to work on tap length bigger than 32??</DIV> <DIV></DIV> <DIV>So would that mean that i would need to make use of the delay line. Any example on the use of the delay line? Sorry for i'm not very familar with DSP.:smileysad:</DIV> <DIV></DIV> <DIV>Thanxs in advance.</DIV><P>Message Edited by aldebaran on <SPAN class="date_text">02-15-2004</SPAN> <SPAN class="time_text">01:19 AM</SPAN></P> Sun, 15 Feb 2004 17:13:34 GMT https://community.intel.com/t5/Intel-Integrated-Performance/FIR-LMS/m-p/970227#M20515 aldebaran 2004-02-15T17:13:34Z https://community.intel.com/t5/Intel-Integrated-Performance/FIR-LMS/m-p/970228#M20516 <DIV>Dear Customer,<BR />Could you please provide us more details on this report for the failure on calling FIRLMS functions by submitting an issue via Intel Premier Support at <A href="https://premier.intel.com" target="_blank">https://premier.intel.com</A>? Also it would be helpful to supply your test case that can replicate this problem, and our support staff will look into this problem.</DIV> <DIV></DIV> <DIV>Thanks,<BR />Ying <BR />Intel IPP</DIV> Wed, 18 Feb 2004 11:36:43 GMT https://community.intel.com/t5/Intel-Integrated-Performance/FIR-LMS/m-p/970228#M20516 Ying_S_Intel 2004-02-18T11:36:43Z https://community.intel.com/t5/Intel-Integrated-Performance/FIR-LMS/m-p/970229#M20517 <P>no limitation in num of LMS coeffs. But the more taps the less mu value should be</P> <DIV></DIV> Fri, 20 Feb 2004 01:57:40 GMT https://community.intel.com/t5/Intel-Integrated-Performance/FIR-LMS/m-p/970229#M20517 borix 2004-02-20T01:57:40Z