https://community.intel.com/t5/Intel-Integrated-Performance/Cache-usage-for-a-DSP-program-implemented-with-IPP/m-p/990488#M22243 Hello,<BR /><BR />I am currently building a real-time multiprocessor scheduling algorithm that will preempt<BR />tasks and move them between processors frequently. One of our biggest concerns is that<BR />there will be a serious cache hit whenever a task moves between processors. Our target application<BR />is a DSP program, and as is my understand such programs typically have a small cache footprint. I was wondering, if we were to move our DSP program over to the IPP, how large would the cache footprint be?<BR /><BR />Thanks for the help,<BR /><BR />Aaron Wed, 25 May 2005 01:34:36 GMT block1 2005-05-25T01:34:36Z https://community.intel.com/t5/Intel-Integrated-Performance/Cache-usage-for-a-DSP-program-implemented-with-IPP/m-p/990488#M22243 Hello,<BR /><BR />I am currently building a real-time multiprocessor scheduling algorithm that will preempt<BR />tasks and move them between processors frequently. One of our biggest concerns is that<BR />there will be a serious cache hit whenever a task moves between processors. Our target application<BR />is a DSP program, and as is my understand such programs typically have a small cache footprint. I was wondering, if we were to move our DSP program over to the IPP, how large would the cache footprint be?<BR /><BR />Thanks for the help,<BR /><BR />Aaron Wed, 25 May 2005 01:34:36 GMT https://community.intel.com/t5/Intel-Integrated-Performance/Cache-usage-for-a-DSP-program-implemented-with-IPP/m-p/990488#M22243 block1 2005-05-25T01:34:36Z https://community.intel.com/t5/Intel-Integrated-Performance/Cache-usage-for-a-DSP-program-implemented-with-IPP/m-p/990489#M22244 <DIV>Hi Aaron,</DIV> <DIV></DIV> <DIV>I think it is not related to IPP directly. You can write program which work with memory in efficient way with or without using IPP. Generally speaking, you should reduce each task memory requirement to not allow one taskloadallcache memory.</DIV> <DIV></DIV> <DIV>Regards,</DIV> <DIV> Vladimir</DIV> Wed, 25 May 2005 01:59:10 GMT https://community.intel.com/t5/Intel-Integrated-Performance/Cache-usage-for-a-DSP-program-implemented-with-IPP/m-p/990489#M22244 Vladimir_Dudnik 2005-05-25T01:59:10Z