topic FFT Order Limitations? in Intel® Integrated Performance Primitives

FFT Order Limitations?

emhjohnson — Thu, 24 Jun 2010 15:11:01 GMT

Hi,

I cannot seem to find documentation for the minimum and maximum FFT orders supported by IPP.

http://software.intel.com/en-us/articles/mkl-ipp-choosing-an-fft/suggests a maximum order (for DFT) of 2^29 (no mention of the range supported for FFT, aside from powers of 2).

http://software.intel.com/en-us/forums/showthread.php?t=60410suggests a maximum order of 2^27.

Is the range of supported FFT orders 2^1 ... 2^27?

Where can I find this information?

Thanks,

Eric

FFT Order Limitations?

emhjohnson — Fri, 25 Jun 2010 19:27:39 GMT

To answer my own question, I used the lovely trial and error code below (and managed a segfault):

Code:


#include 
#include 
#include 
#include 
#include 

static
const char * ippStatusErrStr(IppStatus status)
{
    switch (status)
    {
        case ippStsNullPtrErr:   return "IPP Null Pointer Error";
        case ippStsFftOrderErr:  return "IPP FFT Order Error";
        case ippStsFftFlagErr:   return "IPP FFT Flag Error";
        case ippStsMemAllocErr:  return "IPP Memory Allocate Error";
        default:                 return "Unrecognized IPP Error";
    };
}

int main(int argc, char **argv)
{
    int n;

    for (n = 1; n < 33; n++)
    {
        IppStatus status;
        IppsFFTSpec_R_32f *spec;

        status = ippsFFTInitAlloc_R_32f (&spec,
                                         n,
                                         IPP_FFT_DIV_INV_BY_N,
                                         ippAlgHintNone);

        if (status != ippStsNoErr)
        {
            printf ("Error for order %d: %s\n", n, ippStatusErrStr(status));
        }
        else
        {
            printf ("Created order %d R_32f input FFT\n", n);
            ippsFFTFree_R_32f (spec);
        }
    }
    
    return 0;
}

Output:


Created order 1 R_32f input FFT
Created order 2 R_32f input FFT
Created order 3 R_32f input FFT
Created order 4 R_32f input FFT
Created order 5 R_32f input FFT
Created order 6 R_32f input FFT
Created order 7 R_32f input FFT
Created order 8 R_32f input FFT
Created order 9 R_32f input FFT
Created order 10 R_32f input FFT
Created order 11 R_32f input FFT
Created order 12 R_32f input FFT
Created order 13 R_32f input FFT
Created order 14 R_32f input FFT
Created order 15 R_32f input FFT
Created order 16 R_32f input FFT
Created order 17 R_32f input FFT
Created order 18 R_32f input FFT
Created order 19 R_32f input FFT
Created order 20 R_32f input FFT
Created order 21 R_32f input FFT
Created order 22 R_32f input FFT
Created order 23 R_32f input FFT
Created order 24 R_32f input FFT
Created order 25 R_32f input FFT
Created order 26 R_32f input FFT
Created order 27 R_32f input FFT
Error for order 28: IPP Memory Allocate Error
Segmentation fault

-Eric

I had a 32 bit app that i

Mesbah__Samy — Wed, 20 Nov 2019 16:32:48 GMT

I had a 32 bit app that I converted to x64 and instead of windowing smaller FFTs for most data I need I can use a single FFT that is 27th order, sometimes 28th or 29th.

I am using VS2019 C++, IPP 2019 update 5, dynamically linked.

I am using the same build setup on my office PC (win 10 pro 1903, core i7-7700, 32GB RAM) and home PC (win 10 pro 1903, core i5-2500, 16GB RAM) and the same release compiles on both machines as well.

Here is the strange part:

The initial call to set up the 64f FFT:

			status = ippsFFTGetSize_R_64f(useOrder, IPP_FFT_DIV_INV_BY_N, ippAlgHintAccurate, &specSize, &specBufferSize, &scratchBufferSize);

The lesser spec machine (core i5-2500) allows a maximum FFT order of 28, after which status is -17 (invalid FFT order)

The higher spec machine (core i7-7700) allows a maximum FFT order of 27, after which status is -17.

Is there a rationale for why a 7th gen processor would have this limitation compared to a 2nd gen one? Also I know "ippAlgHintAccurate" is ignored for x64 since it wont ever use the FPU but I also have win32 configs of the same project which can work with smaller windows.

I am curious what determines the max FFT order, and quite frankly for x64 this shouldn't even be limited to 27/28. On the plus side even a 28th order FFT on a core i5-2500 is extremely fast.

Hi Samy.

Andrey_B_Intel — Fri, 22 Nov 2019 16:35:15 GMT

Hi Samy.

I confirm your issue. The "Core i5-2500" has AVX instruction set while "Core i7-7700" has AVX2. IPP has two branches for them and avx2 supports 2^27 only. We will fix the bug in one on the next IPP releases to support 2^28. As a workaround, you can manually switch IPP to run AVX code on "Core i7-7700" but it may affect performance.

    Ipp64u defaultFeatures;
    ippGetCpuFeatures(&defaultFeatures, 0);
    defaultFeatures &= (ippCPUID_AVX2-1);
    status =  ippSetCpuFeatures(defaultFeatures);

Thanks for your feedback.