topic If this function returns non in Intel® Integrated Performance Primitives

ippInit() returns ippStsUnknownFeature

Jeongkyu_K_ — Fri, 04 Nov 2016 04:14:56 GMT

I recently installed the latest version of IPP and experienced that ippInit() returns ippStsUnknownFeature. The return code is not mentioned in the reference documentation below. https://software.intel.com/en-us/node/502032 IPP functions work well in spite of the error, but I wonder if there is a way to avoid it.

If this function returns non

Gennady_F_Intel — Fri, 04 Nov 2016 05:24:00 GMT

If this function returns non declared value, that's means this is an error. Could you get more details. Are you talking about IPP 2017.update1? this is the latest version of IPP. and What is the CPU type you working on? Is that Lin, Win or OS X ?

Gennady,

Jeongkyu_K_ — Fri, 04 Nov 2016 05:35:53 GMT

Gennady, It happens on Windows 10 and CPU is Intel Core i7-6700@3.4GHz. FYI, I pasted the output from IPP sample. ippCore 2017.0.1 (r53196) Features supported by CPU by IPP ----------------------------------------- ippCPUID_MMX = Y Y Intel(R) Architecture MMX technology supported ippCPUID_SSE = Y Y Intel(R) Streaming SIMD Extensions ippCPUID_SSE2 = Y Y Intel(R) Streaming SIMD Extensions 2 ippCPUID_SSE3 = Y Y Intel(R) Streaming SIMD Extensions 3 ippCPUID_SSSE3 = Y Y Intel(R) Supplemental Streaming SIMD Extensions 3 ippCPUID_MOVBE = Y Y The processor supports MOVBE instruction ippCPUID_SSE41 = Y Y Intel(R) Streaming SIMD Extensions 4.1 ippCPUID_SSE42 = Y Y Intel(R) Streaming SIMD Extensions 4.2 ippCPUID_AVX = Y Y Intel(R) Advanced Vector Extensions instruction set ippAVX_ENABLEDBYOS = Y Y The operating system supports Intel(R) AVX ippCPUID_AES = Y Y Intel(R) AES instruction ippCPUID_SHA = N N Intel(R) SHA new instructions ippCPUID_CLMUL = Y Y PCLMULQDQ instruction ippCPUID_RDRAND = Y Y Read Random Number instructions ippCPUID_F16C = Y Y Float16 instructions ippCPUID_AVX2 = Y Y Intel(R) Advanced Vector Extensions 2 instruction set ippCPUID_AVX512F = N N Intel(R) Advanced Vector Extensions 3.1 instruction set ippCPUID_AVX512CD = N N Intel(R) Advanced Vector Extensions CD (Conflict Detection) instruction set ippCPUID_AVX512ER = N N Intel(R) Advanced Vector Extensions ER instruction set ippCPUID_ADCOX = Y Y ADCX and ADOX instructions ippCPUID_RDSEED = Y Y The RDSEED instruction ippCPUID_PREFETCHW = Y Y The PREFETCHW instruction ippCPUID_KNC = N N Intel« Xeon PhiÖ Coprocessor instruction set Best, Jeongkyu

Hi Jeongkyu,

Zhen_Z_Intel — Fri, 04 Nov 2016 07:21:33 GMT

Hi Jeongkyu,

Did you use ippSetCpuFeatures function in your code, because the ippStsUnknownFeature should be the return value of that function. Normally, the i7 6700 could support SSE4.1/SSE4.2, AVX2. Would you mind share your test code let me know how your process for setting/getting features.

Best regards,
Fiona

Hi Fiona,

Jeongkyu_K_ — Fri, 04 Nov 2016 11:50:52 GMT

Hi Fiona, I also thought it is weird to get the error from ippInit(). The issue could be reproduced using a simple example from IPP SDK so I attached the code. Best, Jeongkyu

Hi Jeongkyu,

Zhen_Z_Intel — Mon, 07 Nov 2016 01:47:26 GMT

Hi Jeongkyu,

On my side, there's no any problem of ippInit. I wonder what is the return value (integer value) of ippInit you get on your machine? And how could you find the integer value represents ippStsUnknownFeature? Because, seems ippInit do not have an output value called ippStsUnknownFeature.

regards,
Fiona

Hi Fiona,

Jeongkyu_K_ — Mon, 07 Nov 2016 02:27:38 GMT

Hi Fiona, The return value of ippInit() on my side is 50 as integer, which seems to represent ippStsUnknownFeature based on IppStatus enum definition at ipptypes.h. By the way, I tried to refresh my development environment to eliminate any possible side effects by re-installing Windows 10, Visual Studio 2015 and Intel IPP SDK, but result was same with only those tools installed. :-( Best, Jeongkyu

Hi Jeongkyu,

Igor_A_Intel — Mon, 07 Nov 2016 08:54:40 GMT

Hi Jeongkyu,

it's just a warning that your CPU has some advanced feature(s), that is(are) not known(supported) by IPP version you currently use. This is not a problem for you, this is just a reminder that this(these) "unknown" feature(s) can be supported in the next IPP versions/updates and possibly add your applications additional performance:

#define PX_MSK    ( 0 )
#define MMX_MSK   ( ippCPUID_MMX )
#define SSE_MSK   ( MMX_MSK   | ippCPUID_SSE     )
#define SSE2_MSK ( SSE_MSK   | ippCPUID_SSE2    )
#define SSE3_MSK ( SSE2_MSK | ippCPUID_SSE3    )
#define SSSE3_MSK ( SSE3_MSK | ippCPUID_SSSE3   )
#define ATOM_MSK ( SSE3_MSK | ippCPUID_SSSE3 | ippCPUID_MOVBE )
#define SSE41_MSK ( SSSE3_MSK | ippCPUID_SSE41   )
#define SSE42_MSK ( SSE41_MSK | ippCPUID_SSE42   )
#define AVX_MSK   ( SSE42_MSK | ippCPUID_AVX     )
#define AVX2_MSK ( AVX_MSK   | ippCPUID_AVX2    )
#define AVX3X_MSK ( AVX2_MSK | ippCPUID_AVX512F | ippCPUID_AVX512CD | ippCPUID_AVX512VL | ippCPUID_AVX512BW | ippCPUID_AVX512DQ )
#define AVX3M_MSK ( AVX2_MSK | ippCPUID_AVX512F | ippCPUID_AVX512CD | ippCPUID_AVX512PF | ippCPUID_AVX512ER )
#define UNKNOWN_FEATURE ((((((((((((((( IPP_MAX_64U ^ AVX3X_MSK )^ippCPUID_AVX512PF)^ippCPUID_AVX512ER)^ippAVX_ENABLEDBYOS)\
                          ^ippCPUID_AES)^ippCPUID_CLMUL)^ippCPUID_ABR)^ippCPUID_RDRAND)^ippCPUID_F16C)^ippCPUID_ADCOX)\
                          ^ippCPUID_RDSEED)^ippCPUID_PREFETCHW)^ippCPUID_SHA)^ippCPUID_KNC) ^ippCPUID_MOVBE )

Could show me an output from something like cpuZ? In order to understand which features your cpu has.

regards, Igor

Hi Igor,

Jeongkyu_K_ — Mon, 07 Nov 2016 09:11:12 GMT

Hi Igor, Thank you for your comment. Then I will treat ippStsUnknownFeature as non-error return value. For my CPU information, I pasted the processor information from CPU Z. Processors Information ------------------------------------------------------------------------- Processor 1 ID = 0 Number of cores 4 (max 4) Number of threads 8 (max 8) Name Intel Core i7 6700 Codename Skylake Specification Intel(R) Core(TM) i7-6700 CPU @ 3.40GHz Package (platform ID) Socket 1151 LGA (0x1) CPUID 6.E.3 Extended CPUID 6.5E Core Stepping R0 Technology 14 nm TDP Limit 65.0 Watts Tjmax 100.0 °C Core Speed 802.2 MHz Multiplier x Bus Speed 8.0 x 100.3 MHz Stock frequency 3400 MHz Instructions sets MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, EM64T, AES, AVX, AVX2, FMA3, TSX L1 Data cache 4 x 32 KBytes, 8-way set associative, 64-byte line size L1 Instruction cache 4 x 32 KBytes, 8-way set associative, 64-byte line size L2 cache 4 x 256 KBytes, 4-way set associative, 64-byte line size L3 cache 8 MBytes, 16-way set associative, 64-byte line size FID/VID Control yes Turbo Mode supported, enabled Max non-turbo ratio 34x Max turbo ratio 40x Max efficiency ratio 8x O/C bins none Ratio 1 core 40x Ratio 2 cores 40x Ratio 3 cores 40x Ratio 4 cores 40x TSC 3408.0 MHz TSC_24 24.0 MHz APERF 3833.9 MHz MPERF 3409.1 MHz IA Voltage Mode PCU adaptive IA Voltage Offset 0 mV GT Voltage Mode PCU adaptive GT Voltage Offset 0 mV LLC/Ring Voltage Mode PCU adaptive LLC/Ring Voltage Offset 0 mV Agent Voltage Mode PCU adaptive Agent Voltage Offset 0 mV Temperature 0 24 degC (75 degF) (Core #0) Temperature 1 21 degC (69 degF) (Core #1) Temperature 2 18 degC (64 degF) (Core #2) Temperature 3 19 degC (66 degF) (Core #3) Temperature 4 27 degC (80 degF) (Package) Voltage 0 1.10 Volts (VID) Voltage 1 +0.00 Volts (IA Offset) Voltage 2 +0.00 Volts (GT Offset) Voltage 3 +0.00 Volts (LLC/Ring Offset) Voltage 4 +0.00 Volts (System Agent Offset) Power 0 14.58 W (Package) Power 1 3.42 W (IA Cores) Power 2 n.a. (GT) Power 3 11.16 W (Uncore) Power 4 0.95 W (DRAM) Clock Speed 0 802.15 MHz (Core #0) Clock Speed 1 3409.15 MHz (Core #1) Clock Speed 2 802.15 MHz (Core #2) Clock Speed 3 3409.15 MHz (Core #3) Best, Jeongkyu

Ok, thank you,

Igor_A_Intel — Mon, 07 Nov 2016 09:45:13 GMT

Ok, thank you,

so you have SkyLake. I found the root of this warning - it's MPX (https://en.wikipedia.org/wiki/Intel_MPX) feature that is analyzed during ippInit stage, but is not a part of "UNKNOWN" feature test above - will be fixed in the next IPP release or update. Anyway MPX is system/kernel-related instruction set that can't be used by IPP - therefore don't pay attention on this warning, please.

regards, Igor

PS what is the purpose of calling ippInit()? It's a rudiment since IPP 9.0 - now library performs auto-initialization itself during the first call of any IPP function (that is not from ippCore domain).

Igor,

Jeongkyu_K_ — Mon, 07 Nov 2016 09:56:10 GMT

Igor, Thank you for the confirmation. I found the issue while I was tracing the existing code, which might be written before IPP 9.0 was released. I will check with my coworker if we can safely remove ippInit() call. Best, Jeongkyu