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    <title>topic ipprWarpAffine bug in Intel® Integrated Performance Primitives</title>
    <link>https://community.intel.com/t5/Intel-Integrated-Performance/ipprWarpAffine-bug/m-p/1125623#M25646</link>
    <description>&lt;P&gt;&amp;nbsp;&lt;/P&gt;

&lt;P&gt;I'm running tests on ipprWarpAffine and get failures for certain permutation matrices.&amp;nbsp;&lt;/P&gt;

&lt;P&gt;My IPP build is 58644 (April 6, 2018). I'm running on Windows 7 (Intel Core i7) and using the ia32_win IPP libraries.&lt;/P&gt;

&lt;P&gt;Below is a simple example to illustrate the problem.&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;

&lt;PRE class="brush:cpp;"&gt;void TestWarpAffine()
{
	double coefs[3][4] ={{0.0, 0.0, 1.0, 0.0}, {1.0, 0.0, 0.0, 0.0}, {0.0, 1.0, 0.0, 0.0}};
	unsigned char in[27] ={0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26};
	unsigned char out[27] ={0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};

	IpprVolume srcSize ={3,3,3}, dstSize ={3,3,3};
	IpprCuboid srcVOI ={0,0,0,3,3,3}, dstVOI ={0,0,0,3,3,3};

	//Step 1: Allocate buffer
	int nBufferSize = 0;
	IppStatus sts = ipprWarpAffineGetBufSize(srcSize, srcVOI, dstVOI, coefs, 1, ippLinear, &amp;amp;nBufferSize); //1 means 1 channel
	ASSERT(sts == ippStsOk &amp;amp;&amp;amp; nBufferSize &amp;gt;= 0);
	nBufferSize = __max(nBufferSize, 10); //Protect against allocating 0 bytes
	Ipp8u* pBuffer = ippsMalloc_8u(nBufferSize);
	ASSERT(pBuffer != NULL);

	//Step 2: Warp
	sts = ipprWarpAffine_8u_C1V(in, srcSize, 3, 9, srcVOI, out, 3, 9, dstVOI, coefs, ippLinear, pBuffer); //3 bytes between rows, 9 bytes between planes
	ippsFree(pBuffer);
	ASSERT(sts == ippStsOk); //Will get sts == -56

	const IppLibraryVersion* pVer = ippGetLibVersion();
}&lt;/PRE&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Fri, 07 Sep 2018 22:48:21 GMT</pubDate>
    <dc:creator>Ken_Thornton</dc:creator>
    <dc:date>2018-09-07T22:48:21Z</dc:date>
    <item>
      <title>ipprWarpAffine bug</title>
      <link>https://community.intel.com/t5/Intel-Integrated-Performance/ipprWarpAffine-bug/m-p/1125623#M25646</link>
      <description>&lt;P&gt;&amp;nbsp;&lt;/P&gt;

&lt;P&gt;I'm running tests on ipprWarpAffine and get failures for certain permutation matrices.&amp;nbsp;&lt;/P&gt;

&lt;P&gt;My IPP build is 58644 (April 6, 2018). I'm running on Windows 7 (Intel Core i7) and using the ia32_win IPP libraries.&lt;/P&gt;

&lt;P&gt;Below is a simple example to illustrate the problem.&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;

&lt;PRE class="brush:cpp;"&gt;void TestWarpAffine()
{
	double coefs[3][4] ={{0.0, 0.0, 1.0, 0.0}, {1.0, 0.0, 0.0, 0.0}, {0.0, 1.0, 0.0, 0.0}};
	unsigned char in[27] ={0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26};
	unsigned char out[27] ={0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};

	IpprVolume srcSize ={3,3,3}, dstSize ={3,3,3};
	IpprCuboid srcVOI ={0,0,0,3,3,3}, dstVOI ={0,0,0,3,3,3};

	//Step 1: Allocate buffer
	int nBufferSize = 0;
	IppStatus sts = ipprWarpAffineGetBufSize(srcSize, srcVOI, dstVOI, coefs, 1, ippLinear, &amp;amp;nBufferSize); //1 means 1 channel
	ASSERT(sts == ippStsOk &amp;amp;&amp;amp; nBufferSize &amp;gt;= 0);
	nBufferSize = __max(nBufferSize, 10); //Protect against allocating 0 bytes
	Ipp8u* pBuffer = ippsMalloc_8u(nBufferSize);
	ASSERT(pBuffer != NULL);

	//Step 2: Warp
	sts = ipprWarpAffine_8u_C1V(in, srcSize, 3, 9, srcVOI, out, 3, 9, dstVOI, coefs, ippLinear, pBuffer); //3 bytes between rows, 9 bytes between planes
	ippsFree(pBuffer);
	ASSERT(sts == ippStsOk); //Will get sts == -56

	const IppLibraryVersion* pVer = ippGetLibVersion();
}&lt;/PRE&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 07 Sep 2018 22:48:21 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Integrated-Performance/ipprWarpAffine-bug/m-p/1125623#M25646</guid>
      <dc:creator>Ken_Thornton</dc:creator>
      <dc:date>2018-09-07T22:48:21Z</dc:date>
    </item>
    <item>
      <title>is that 64 or 32 bit code or</title>
      <link>https://community.intel.com/t5/Intel-Integrated-Performance/ipprWarpAffine-bug/m-p/1125624#M25647</link>
      <description>&lt;P&gt;is that 64 or 32 bit code or both?&lt;/P&gt;</description>
      <pubDate>Sat, 08 Sep 2018 02:41:47 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Integrated-Performance/ipprWarpAffine-bug/m-p/1125624#M25647</guid>
      <dc:creator>Gennady_F_Intel</dc:creator>
      <dc:date>2018-09-08T02:41:47Z</dc:date>
    </item>
    <item>
      <title>-56 error code means that</title>
      <link>https://community.intel.com/t5/Intel-Integrated-Performance/ipprWarpAffine-bug/m-p/1125625#M25648</link>
      <description>&lt;P&gt;-56 error code means that&amp;nbsp;&lt;SPAN style="font-size: 13.008px;"&gt;ippStsCoeffErr&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; determinant of the transform matrix Aij is equal to zero. if you will fix this - your case will work.&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Sat, 08 Sep 2018 03:17:01 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Integrated-Performance/ipprWarpAffine-bug/m-p/1125625#M25648</guid>
      <dc:creator>Gennady_F_Intel</dc:creator>
      <dc:date>2018-09-08T03:17:01Z</dc:date>
    </item>
    <item>
      <title>I know what the error code</title>
      <link>https://community.intel.com/t5/Intel-Integrated-Performance/ipprWarpAffine-bug/m-p/1125626#M25649</link>
      <description>&lt;DIV&gt;Gennady,&lt;/DIV&gt;

&lt;DIV&gt;No the determinant is 1, not 0. So it is invertible.&lt;/DIV&gt;

&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;

&lt;DIV&gt;&lt;A href="https://software.intel.com/en-us/ipp-dev-reference-warpaffine" target="_blank"&gt;https://software.intel.com/en-us/ipp-dev-reference-warpaffine&lt;/A&gt;&lt;/DIV&gt;

&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;

&lt;DIV&gt;If p is a 3D point in the source volume and q is a 3D point in the destination volume:&lt;/DIV&gt;

&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;

&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; | 0 0 1 |&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;| 0 |&lt;/DIV&gt;

&lt;DIV&gt;q = | 1 0 0 | p + | 0 |&lt;/DIV&gt;

&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; | 0 1 0 |&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;| 0 |&lt;/DIV&gt;

&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;

&lt;DIV&gt;The inverse transformation is:&lt;/DIV&gt;

&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;

&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;| 0 1 0 |&lt;/DIV&gt;

&lt;DIV&gt;p =&amp;nbsp; | 0 0 1 | q&lt;/DIV&gt;

&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;| 1 0 0 |&lt;/DIV&gt;

&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&amp;nbsp;&lt;/DIV&gt;

&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;-1&lt;/DIV&gt;

&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; | 0 1 0 |&amp;nbsp; &amp;nbsp; &amp;nbsp; | 0 0 1 |&lt;/DIV&gt;

&lt;DIV&gt;Since&amp;nbsp; &amp;nbsp;| 0 0 1 |&amp;nbsp; =&amp;nbsp; | 1 0 0 |&lt;/DIV&gt;

&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; | 1 0 0 |&amp;nbsp; &amp;nbsp; &amp;nbsp; | 0 1 0 |&lt;/DIV&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 10 Sep 2018 13:25:57 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Integrated-Performance/ipprWarpAffine-bug/m-p/1125626#M25649</guid>
      <dc:creator>Ken_Thornton</dc:creator>
      <dc:date>2018-09-10T13:25:57Z</dc:date>
    </item>
    <item>
      <title>Ken, we confirmed the problem</title>
      <link>https://community.intel.com/t5/Intel-Integrated-Performance/ipprWarpAffine-bug/m-p/1125627#M25650</link>
      <description>&lt;P&gt;Ken, we confirmed the problem and will add the fix into one of the nearest updates. We will keep you updated with the status of this issue. Thanks for report.&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 12 Sep 2018 08:56:18 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Integrated-Performance/ipprWarpAffine-bug/m-p/1125627#M25650</guid>
      <dc:creator>Gennady_F_Intel</dc:creator>
      <dc:date>2018-09-12T08:56:18Z</dc:date>
    </item>
    <item>
      <title>the fix of the problem</title>
      <link>https://community.intel.com/t5/Intel-Integrated-Performance/ipprWarpAffine-bug/m-p/1125628#M25651</link>
      <description>&lt;P&gt;the fix of the problem available since IPP 2019 u1 and the latest 2020 versions as well.&lt;/P&gt;</description>
      <pubDate>Thu, 07 May 2020 09:31:32 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Integrated-Performance/ipprWarpAffine-bug/m-p/1125628#M25651</guid>
      <dc:creator>Gennady_F_Intel</dc:creator>
      <dc:date>2020-05-07T09:31:32Z</dc:date>
    </item>
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