<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re:Replacement for ippiRotate_32f_C1R in Intel® Integrated Performance Primitives</title>
    <link>https://community.intel.com/t5/Intel-Integrated-Performance/Replacement-for-ippiRotate-32f-C1R/m-p/1271558#M27632</link>
    <description>&lt;P&gt;Hi ChristinaLabay,&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Thanks for reaching out to us.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;We are working on it internally. We will get back to you.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Arpita&lt;/P&gt;&lt;BR /&gt;</description>
    <pubDate>Wed, 07 Apr 2021 10:50:23 GMT</pubDate>
    <dc:creator>ArpitaP_Intel</dc:creator>
    <dc:date>2021-04-07T10:50:23Z</dc:date>
    <item>
      <title>Replacement for ippiRotate_32f_C1R</title>
      <link>https://community.intel.com/t5/Intel-Integrated-Performance/Replacement-for-ippiRotate-32f-C1R/m-p/1270951#M27629</link>
      <description>&lt;P&gt;We have recently updated our ippi version, and need to replace ippiRotate_32f_C1R. I have found this post, &lt;A href="https://community.intel.com/t5/Intel-Integrated-Performance/How-to-replace-ipp-functions-ippiRotate-32f-C1R-and/td-p/1082539" target="_blank" rel="noopener"&gt;https://community.intel.com/t5/Intel-Integrated-Performance/How-to-replace-ipp-functions-ippiRotate-32f-C1R-and/td-p/1082539&lt;/A&gt;, but the links listed are no longer valid. From my understanding, we will need to use a combination of ippiWarpAffine functions and the ippiRotateTranslate functions. I found a sample document for ippiRotate_8u_C3R (attached), and attempted to implement a solution from that, but we are getting different results than our previous version.&lt;/P&gt;
&lt;P&gt;This is what we have written as our replacement:&lt;/P&gt;
&lt;DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;IppStatus&amp;nbsp;status;&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;IppiWarpSpec*&amp;nbsp;pSpec&amp;nbsp;=&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;0&lt;/SPAN&gt;&lt;SPAN&gt;;&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;double&lt;/SPAN&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;coeffs&lt;/SPAN&gt;&lt;SPAN&gt;[&lt;/SPAN&gt;&lt;SPAN&gt;2&lt;/SPAN&gt;&lt;SPAN&gt;][&lt;/SPAN&gt;&lt;SPAN&gt;3&lt;/SPAN&gt;&lt;SPAN&gt;]&amp;nbsp;=&amp;nbsp;{&lt;/SPAN&gt;&lt;SPAN&gt;0&lt;/SPAN&gt;&lt;SPAN&gt;};&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;int&lt;/SPAN&gt;&lt;SPAN&gt;&amp;nbsp;specSize&amp;nbsp;=&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;0&lt;/SPAN&gt;&lt;SPAN&gt;,&amp;nbsp;initSize&amp;nbsp;=&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;0&lt;/SPAN&gt;&lt;SPAN&gt;,&amp;nbsp;bufSize&amp;nbsp;=&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;0&lt;/SPAN&gt;&lt;SPAN&gt;;&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;Ipp32f*&amp;nbsp;pBuffer&amp;nbsp;&amp;nbsp;=&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;0&lt;/SPAN&gt;&lt;SPAN&gt;;&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;IppiPoint&amp;nbsp;dstOffset&amp;nbsp;=&amp;nbsp;{&lt;/SPAN&gt;&lt;SPAN&gt;0&lt;/SPAN&gt;&lt;SPAN&gt;,&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;0&lt;/SPAN&gt;&lt;SPAN&gt;};&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;Ipp64f&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;pBorderValue&lt;/SPAN&gt;&lt;SPAN&gt;[&lt;/SPAN&gt;&lt;SPAN&gt;1&lt;/SPAN&gt;&lt;SPAN&gt;]&amp;nbsp;=&amp;nbsp;{&lt;/SPAN&gt;&lt;SPAN&gt;0&lt;/SPAN&gt;&lt;SPAN&gt;};&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;BR /&gt;
&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;status&amp;nbsp;=&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;ippiGetRotateTransform&lt;/SPAN&gt;&lt;SPAN&gt;&amp;nbsp;(angle,&amp;nbsp;xShift,&amp;nbsp;yShift,&amp;nbsp;(&lt;/SPAN&gt;&lt;SPAN&gt;double&lt;/SPAN&gt;&lt;SPAN&gt;(*)[&lt;/SPAN&gt;&lt;SPAN&gt;3&lt;/SPAN&gt;&lt;SPAN&gt;])coeffs);&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;if&lt;/SPAN&gt;&lt;SPAN&gt;(status&amp;nbsp;!=&amp;nbsp;ippStsNoErr)&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;return&lt;/SPAN&gt;&lt;SPAN&gt;&amp;nbsp;status;&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;status&amp;nbsp;=&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;ippiWarpAffineGetSize&lt;/SPAN&gt;&lt;SPAN&gt;(srcSize,&amp;nbsp;dstSize,&amp;nbsp;ipp32f,&amp;nbsp;coeffs,&amp;nbsp;ippLinear,&amp;nbsp;ippWarpForward,&amp;nbsp;ippBorderRepl,&amp;nbsp;&amp;amp;specSize,&amp;nbsp;&amp;amp;initSize);&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;if&lt;/SPAN&gt;&lt;SPAN&gt;(status&amp;nbsp;!=&amp;nbsp;ippStsNoErr)&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;return&lt;/SPAN&gt;&lt;SPAN&gt;&amp;nbsp;status;&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;pSpec&amp;nbsp;=&amp;nbsp;(IppiWarpSpec*)&lt;/SPAN&gt;&lt;SPAN&gt;ippsMalloc_32f&lt;/SPAN&gt;&lt;SPAN&gt;(specSize);&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;status&amp;nbsp;=&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;ippiWarpAffineLinearInit&lt;/SPAN&gt;&lt;SPAN&gt;(srcSize,&amp;nbsp;dstSize,&amp;nbsp;ipp32f,&amp;nbsp;coeffs,&amp;nbsp;ippWarpForward,&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;1&lt;/SPAN&gt;&lt;SPAN&gt;,&amp;nbsp;ippBorderRepl,&amp;nbsp;pBorderValue,&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;0&lt;/SPAN&gt;&lt;SPAN&gt;,&amp;nbsp;pSpec);&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;if&lt;/SPAN&gt;&lt;SPAN&gt;(status&amp;nbsp;!=&amp;nbsp;ippStsNoErr)&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;{&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;ippsFree&lt;/SPAN&gt;&lt;SPAN&gt;(pSpec);&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;return&lt;/SPAN&gt;&lt;SPAN&gt;&amp;nbsp;status;&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;}&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;BR /&gt;
&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;status&amp;nbsp;=&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;ippiWarpGetBufferSize&lt;/SPAN&gt;&lt;SPAN&gt;(pSpec,&amp;nbsp;dstSize,&amp;nbsp;&amp;amp;bufSize);&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;if&lt;/SPAN&gt;&lt;SPAN&gt;(status&amp;nbsp;!=&amp;nbsp;ippStsNoErr)&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;return&lt;/SPAN&gt;&lt;SPAN&gt;&amp;nbsp;status;&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;pBuffer&amp;nbsp;=&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;ippsMalloc_32f&lt;/SPAN&gt;&lt;SPAN&gt;(bufSize);&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;BR /&gt;
&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;status&amp;nbsp;=&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;ippiWarpAffineLinear_32f_C1R&lt;/SPAN&gt;&lt;SPAN&gt;(pSrc,&amp;nbsp;srcStep,&amp;nbsp;pDst,&amp;nbsp;dstStep,&amp;nbsp;dstOffset,&amp;nbsp;dstSize,&amp;nbsp;pSpec,&amp;nbsp;pBuffer);&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;BR /&gt;
&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;ippsFree&lt;/SPAN&gt;&lt;SPAN&gt;(pSpec);&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;ippsFree&lt;/SPAN&gt;&lt;SPAN&gt;(pBuffer);&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;/DIV&gt;</description>
      <pubDate>Mon, 05 Apr 2021 18:39:03 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Integrated-Performance/Replacement-for-ippiRotate-32f-C1R/m-p/1270951#M27629</guid>
      <dc:creator>ChristinaLabay</dc:creator>
      <dc:date>2021-04-05T18:39:03Z</dc:date>
    </item>
    <item>
      <title>Re:Replacement for ippiRotate_32f_C1R</title>
      <link>https://community.intel.com/t5/Intel-Integrated-Performance/Replacement-for-ippiRotate-32f-C1R/m-p/1271558#M27632</link>
      <description>&lt;P&gt;Hi ChristinaLabay,&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Thanks for reaching out to us.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;We are working on it internally. We will get back to you.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Arpita&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Wed, 07 Apr 2021 10:50:23 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Integrated-Performance/Replacement-for-ippiRotate-32f-C1R/m-p/1271558#M27632</guid>
      <dc:creator>ArpitaP_Intel</dc:creator>
      <dc:date>2021-04-07T10:50:23Z</dc:date>
    </item>
    <item>
      <title>Re: Re:Replacement for ippiRotate_32f_C1R</title>
      <link>https://community.intel.com/t5/Intel-Integrated-Performance/Replacement-for-ippiRotate-32f-C1R/m-p/1272466#M27633</link>
      <description>&lt;P&gt;Hi Christina,&lt;/P&gt;
&lt;P&gt;For ippiRotate_32f_C1R replacement, I am attaching a sample file Rotate.c to help you understand the usage of APIs.&lt;/P&gt;
&lt;P&gt;We have a reference manual on how to substitute deprecated IPP functions:&lt;BR /&gt;&lt;A href="https://software.intel.com/content/www/us/en/develop/documentation/ipp-dev-reference/top/volume-2-image-processing/appendix-c-removed-functions-for-image-and-video-processing.html" target="_blank"&gt;https://software.intel.com/content/www/us/en/develop/documentation/ipp-dev-reference/top/volume-2-image-processing/appendix-c-removed-functions-for-image-and-video-processing.html&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;Let us know about your results.&lt;/P&gt;
&lt;P&gt;-&lt;/P&gt;
&lt;P&gt;Abhinav&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 09 Apr 2021 20:28:15 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Integrated-Performance/Replacement-for-ippiRotate-32f-C1R/m-p/1272466#M27633</guid>
      <dc:creator>Abhinav_S_Intel</dc:creator>
      <dc:date>2021-04-09T20:28:15Z</dc:date>
    </item>
    <item>
      <title>Re:Replacement for ippiRotate_32f_C1R</title>
      <link>https://community.intel.com/t5/Intel-Integrated-Performance/Replacement-for-ippiRotate-32f-C1R/m-p/1284457#M27697</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Hope the provided solution worked for you. We will no longer monitor this thread. If you require any additional assistance from Intel, please start a new thread.&amp;nbsp;&lt;/P&gt;&lt;P&gt;Any further interaction in this thread will be considered community only.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Warm Regards,&lt;/P&gt;&lt;P&gt;Abhishek&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Tue, 25 May 2021 11:20:18 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Integrated-Performance/Replacement-for-ippiRotate-32f-C1R/m-p/1284457#M27697</guid>
      <dc:creator>AbhishekD_Intel</dc:creator>
      <dc:date>2021-05-25T11:20:18Z</dc:date>
    </item>
  </channel>
</rss>

