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    <title>topic Re: Problems with using ippiDilateBorder_1u_C1R in Intel® Integrated Performance Primitives</title>
    <link>https://community.intel.com/t5/Intel-Integrated-Performance/Problems-with-using-ippiDilateBorder-1u-C1R/m-p/1314355#M27761</link>
    <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;Thanks for reaching out to us.&lt;/P&gt;
&lt;P&gt;The issue raised by you is reproducible.&lt;/P&gt;
&lt;P&gt;We are looking into it. We will get back to you soon.&lt;/P&gt;
&lt;P&gt;Regards,&lt;/P&gt;
&lt;P&gt;Vidya.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Tue, 14 Sep 2021 06:59:14 GMT</pubDate>
    <dc:creator>VidyalathaB_Intel</dc:creator>
    <dc:date>2021-09-14T06:59:14Z</dc:date>
    <item>
      <title>Problems with using ippiDilateBorder_1u_C1R</title>
      <link>https://community.intel.com/t5/Intel-Integrated-Performance/Problems-with-using-ippiDilateBorder-1u-C1R/m-p/1314122#M27759</link>
      <description>&lt;P&gt;&lt;SPAN class="text-dst"&gt;Hi，&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN class="text-dst"&gt;I am a college student and took the course of basic image processing.&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;SPAN class="text-dst"&gt;So I tested some morphological functions of the ipp library.such as&lt;/SPAN&gt;&lt;SPAN class="text-dst"&gt;&amp;nbsp;the question I submitted last time about ippiMorphOpenBorder &lt;SPAN&gt;and got a satisfactory reply, I am very grateful&lt;/SPAN&gt;.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN class="text-dst"&gt;When I was testing ippiDilateBorder_1u_C1R this time, I noticed that it had two extra parameters: bitOffset.&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;According to the description of the document, I understand it as the offset of src and dst.&lt;SPAN&gt;My tests are as follows:&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;EM&gt;&lt;STRONG&gt;IppiSize roiSize = { 16, 3 };&lt;/STRONG&gt;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;&lt;STRONG&gt;Ipp8u pSrc[80] = { &lt;/STRONG&gt;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;&lt;STRONG&gt;10, 126, 83, 244, 162, 22, 183, 137, 224, 163, 114, 112, 42, 13, 160, 225, &lt;/STRONG&gt;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;&lt;STRONG&gt;39, 106, 206, 197, 105, 21, 189, 110, 79, 0, 99, 134, 41, 75, 51, 69, &lt;/STRONG&gt;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;&lt;STRONG&gt;158, 21, 158, 231, 75, 146, 218, 94, 173, 93, 226, 68, 65, 16, 190, 19, &lt;/STRONG&gt;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;&lt;STRONG&gt;233, 19, 4, 152, 146, 177, 159, 165, 20, 113, 207, 7, 89, 163, 113, 183, &lt;/STRONG&gt;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;&lt;STRONG&gt;194, 57, 129, 85, 198, 216, 221, 209, 221, 47, 75, 108, 156, 136, 190, 223&lt;/STRONG&gt;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;&lt;STRONG&gt;};&lt;/STRONG&gt;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;&lt;STRONG&gt;Ipp8u dst[80] = { 0 };&lt;/STRONG&gt;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;&lt;STRONG&gt;Ipp8u mask[3 * 3] = { 1,1, 1, 1,1, 1, 1, 1,1 };&lt;/STRONG&gt;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;&lt;STRONG&gt;IppiSize maskSize = { 3, 3 };&lt;/STRONG&gt;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;&lt;STRONG&gt;IppiMorphState *spec;&lt;/STRONG&gt;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;&lt;STRONG&gt;Ipp8u *buffer;&lt;/STRONG&gt;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;&lt;STRONG&gt;Ipp32s bufferSize, specSize;&lt;/STRONG&gt;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;&lt;STRONG&gt;ippiMorphologyBorderGetSize_1u_C1R(roiSize, maskSize, &amp;amp;specSize, &amp;amp;bufferSize);&lt;/STRONG&gt;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;&lt;STRONG&gt;spec = (IppiMorphState*)ippsMalloc_8u(specSize);&lt;/STRONG&gt;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;&lt;STRONG&gt;buffer = (Ipp8u*)ippsMalloc_8u(bufferSize);&lt;/STRONG&gt;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;&lt;STRONG&gt;ippiMorphologyBorderInit_1u_C1R(roiSize, mask, maskSize, spec, buffer);&lt;/STRONG&gt;&lt;/EM&gt;&lt;/P&gt;
&lt;P&gt;&lt;EM&gt;&lt;STRONG&gt;IppStatus sts = ippiDilateBorder_1u_C1R(pSrc, 16, 0,dst, 16,0, roiSize, (IppiBorderType)1, 0, spec, buffer);&lt;/STRONG&gt;&lt;/EM&gt;&lt;/P&gt;
&lt;P&gt;&lt;EM&gt;&lt;STRONG&gt;for (int i = 0; i &amp;lt; 5; i++){&lt;/STRONG&gt;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;&lt;STRONG&gt;for (int j = 0; j &amp;lt; 16; j++){&lt;/STRONG&gt;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;&lt;STRONG&gt;printf("%d ", dst[i * 16 + j]);&lt;/STRONG&gt;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;&lt;STRONG&gt;}&lt;/STRONG&gt;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;&lt;STRONG&gt;printf("\n");&lt;/STRONG&gt;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;&lt;STRONG&gt;}&lt;/STRONG&gt;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;&lt;STRONG&gt;printf("\n");&lt;/STRONG&gt;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;&lt;STRONG&gt;printf("\n");&lt;/STRONG&gt;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;&lt;STRONG&gt;printf("%d\n\n\n\n\n", sts);&lt;/STRONG&gt;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;&lt;STRONG&gt;ippsFree(buffer);&lt;/STRONG&gt;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;&lt;STRONG&gt;ippsFree(spec);&lt;/STRONG&gt;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;&lt;STRONG&gt;system("pause");&lt;/STRONG&gt;&lt;/EM&gt;&lt;/P&gt;
&lt;P&gt;When the dstBitOffset is 0, the result is as follows：&lt;/P&gt;
&lt;P&gt;&lt;EM&gt;&lt;STRONG&gt;&lt;SPAN&gt;127 255 0 0 0 0 0 0 0 0 0 0 0 0 0 0&lt;BR /&gt;255 255 0 0 0 0 0 0 0 0 0 0 0 0 0 0&lt;BR /&gt;255 255 0 0 0 0 0 0 0 0 0 0 0 0 0 0&lt;BR /&gt;0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0&lt;BR /&gt;0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0&lt;/SPAN&gt;&lt;/STRONG&gt;&lt;/EM&gt;&lt;/P&gt;
&lt;P&gt;and when&amp;nbsp;the dstBitOffset is 7, the result is as follows：&lt;/P&gt;
&lt;P&gt;&lt;EM&gt;&lt;STRONG&gt;&lt;SPAN&gt;128 191 127 0 0 0 0 0 0 0 0 0 0 0 0 0&lt;BR /&gt;128 255 127 0 0 0 0 0 0 0 0 0 0 0 0 0&lt;BR /&gt;128 255 127 0 0 0 0 0 0 0 0 0 0 0 0 0&lt;BR /&gt;0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0&lt;BR /&gt;0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0&lt;/SPAN&gt;&lt;/STRONG&gt;&lt;/EM&gt;&lt;/P&gt;
&lt;P&gt;It's same as when the dstBitOffset is 0,7bits is offset only when storing.&lt;/P&gt;
&lt;P&gt;But when the&amp;nbsp;dstBitOffset is 8, the result is as follows:&lt;/P&gt;
&lt;P&gt;&lt;EM&gt;&lt;STRONG&gt;0 127 255 0 0 0 0 0 0 0 0 0 0 0 0 0&lt;/STRONG&gt;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;&lt;STRONG&gt;0 254 255 0 0 0 0 0 0 0 0 0 0 0 0 0&lt;/STRONG&gt;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;&lt;STRONG&gt;0 255 255 0 0 0 0 0 0 0 0 0 0 0 0 0&lt;/STRONG&gt;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;&lt;STRONG&gt;0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0&lt;/STRONG&gt;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;&lt;STRONG&gt;0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0&lt;/STRONG&gt;&lt;/EM&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN class="text-dst"&gt;&lt;SPAN class="text-dst"&gt;Instead of offsetting a byte in storage as I thought, the result has changed.&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN class="text-dst"&gt;I don't understand this phenomenon, so I'd like to ask what this BitOffset parameter stands for.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class="text-dst"&gt;Looking forward to your reply,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class="text-dst"&gt;Thanks&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Mon, 13 Sep 2021 11:23:27 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Integrated-Performance/Problems-with-using-ippiDilateBorder-1u-C1R/m-p/1314122#M27759</guid>
      <dc:creator>XDu</dc:creator>
      <dc:date>2021-09-13T11:23:27Z</dc:date>
    </item>
    <item>
      <title>Re: Problems with using ippiDilateBorder_1u_C1R</title>
      <link>https://community.intel.com/t5/Intel-Integrated-Performance/Problems-with-using-ippiDilateBorder-1u-C1R/m-p/1314355#M27761</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;Thanks for reaching out to us.&lt;/P&gt;
&lt;P&gt;The issue raised by you is reproducible.&lt;/P&gt;
&lt;P&gt;We are looking into it. We will get back to you soon.&lt;/P&gt;
&lt;P&gt;Regards,&lt;/P&gt;
&lt;P&gt;Vidya.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 14 Sep 2021 06:59:14 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Integrated-Performance/Problems-with-using-ippiDilateBorder-1u-C1R/m-p/1314355#M27761</guid>
      <dc:creator>VidyalathaB_Intel</dc:creator>
      <dc:date>2021-09-14T06:59:14Z</dc:date>
    </item>
    <item>
      <title>Re: Problems with using ippiDilateBorder_1u_C1R</title>
      <link>https://community.intel.com/t5/Intel-Integrated-Performance/Problems-with-using-ippiDilateBorder-1u-C1R/m-p/1315841#M27770</link>
      <description>&lt;P&gt;Hi,&amp;nbsp; XDu.&lt;/P&gt;
&lt;P&gt;I confirm this issue. dstBitOffset equal 8 means 1 byte of destination offset. As workaround you can add next "if" before calling "ippiDilateBorder_1u_C1R":&lt;/P&gt;
&lt;P&gt;if (dstBitOffset &amp;gt;= &lt;LI-EMOJI id="lia_smiling-face-with-sunglasses" title=":smiling_face_with_sunglasses:"&gt;&lt;/LI-EMOJI&gt; {&lt;BR /&gt;&amp;nbsp; dst = dst + (dstBitOffset &amp;gt;&amp;gt; 3);&lt;BR /&gt;&amp;nbsp; dstBitOffset &amp;amp;= 7;&lt;BR /&gt;}&lt;/P&gt;
&lt;P&gt;We will fix this issue in one of the next IPP releases.&lt;/P&gt;
&lt;P&gt;Andrey&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 20 Sep 2021 09:04:05 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Integrated-Performance/Problems-with-using-ippiDilateBorder-1u-C1R/m-p/1315841#M27770</guid>
      <dc:creator>Andrey_B_Intel</dc:creator>
      <dc:date>2021-09-20T09:04:05Z</dc:date>
    </item>
    <item>
      <title>Re: Problems with using ippiDilateBorder_1u_C1R</title>
      <link>https://community.intel.com/t5/Intel-Integrated-Performance/Problems-with-using-ippiDilateBorder-1u-C1R/m-p/1316349#M27777</link>
      <description>&lt;P&gt;&lt;SPAN&gt;thanks for your reply，but I don't quite understand the meaning of the following code.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;if (dstBitOffset &amp;gt;=&amp;nbsp;&lt;/SPAN&gt;&lt;LI-EMOJI id="lia_smiling-face-with-sunglasses" title=":smiling_face_with_sunglasses:"&gt;&lt;/LI-EMOJI&gt;&lt;SPAN&gt;{&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp; dst = dst + (dstBitOffset &amp;gt;&amp;gt; 3);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp; dstBitOffset &amp;amp;= 7;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;}&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;Do you mean to offset dst dstBitOffset/8 bytes ahead of time when dstBitOffset &amp;gt; = 8?&lt;/P&gt;
&lt;P&gt;But isn't the role of dsiBitOffset to offset every line of dst from the same bit?And whether there is a same question with srcBitOffset?&lt;/P&gt;
&lt;P&gt;Thanks again for the reply,and&amp;nbsp;because I don't know much about the written politeness of English, please forgive me if there is any offense.&lt;/P&gt;
&lt;P&gt;XDu&lt;/P&gt;</description>
      <pubDate>Wed, 22 Sep 2021 02:24:20 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Integrated-Performance/Problems-with-using-ippiDilateBorder-1u-C1R/m-p/1316349#M27777</guid>
      <dc:creator>XDu</dc:creator>
      <dc:date>2021-09-22T02:24:20Z</dc:date>
    </item>
    <item>
      <title>Re:Problems with using ippiDilateBorder_1u_C1R</title>
      <link>https://community.intel.com/t5/Intel-Integrated-Performance/Problems-with-using-ippiDilateBorder-1u-C1R/m-p/1350070#M27893</link>
      <description>&lt;P&gt;XDu,&lt;/P&gt;&lt;P&gt;please check the latest IPP 2021 u5 and let us know if the problem you reported still exists. &lt;/P&gt;&lt;P&gt;thanks,&lt;/P&gt;&lt;P&gt;Gennady&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Mon, 10 Jan 2022 14:50:37 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Integrated-Performance/Problems-with-using-ippiDilateBorder-1u-C1R/m-p/1350070#M27893</guid>
      <dc:creator>Gennady_F_Intel</dc:creator>
      <dc:date>2022-01-10T14:50:37Z</dc:date>
    </item>
    <item>
      <title>Re:Problems with using ippiDilateBorder_1u_C1R</title>
      <link>https://community.intel.com/t5/Intel-Integrated-Performance/Problems-with-using-ippiDilateBorder-1u-C1R/m-p/1352951#M27902</link>
      <description>&lt;P&gt;This issue has been resolved and we will no longer respond to this thread.&amp;nbsp;If you require additional assistance from Intel, please start a new thread.&amp;nbsp;Any further interaction in this thread will be considered community only.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Thu, 20 Jan 2022 06:14:31 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Integrated-Performance/Problems-with-using-ippiDilateBorder-1u-C1R/m-p/1352951#M27902</guid>
      <dc:creator>Gennady_F_Intel</dc:creator>
      <dc:date>2022-01-20T06:14:31Z</dc:date>
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