https://community.intel.com/t5/Intel-Integrated-Performance/L1-dcache-loads-meansing/m-p/1567818#M28618 <P>Regarding the L1-dcache-loads events, Is it only include the memory access instructions submitted? Isthe perfetch included in it ? How about the memory access instructions followed by a wrong&nbsp;<SPAN>branch prediction?</SPAN></P> Wed, 31 Jan 2024 09:15:43 GMT jiadengx 2024-01-31T09:15:43Z https://community.intel.com/t5/Intel-Integrated-Performance/L1-dcache-loads-meansing/m-p/1567818#M28618 <P>Regarding the L1-dcache-loads events, Is it only include the memory access instructions submitted? Isthe perfetch included in it ? How about the memory access instructions followed by a wrong&nbsp;<SPAN>branch prediction?</SPAN></P> Wed, 31 Jan 2024 09:15:43 GMT https://community.intel.com/t5/Intel-Integrated-Performance/L1-dcache-loads-meansing/m-p/1567818#M28618 jiadengx 2024-01-31T09:15:43Z https://community.intel.com/t5/Intel-Integrated-Performance/L1-dcache-loads-meansing/m-p/1568196#M28621 <P>I am not sure if this question is related to IPP library. It seems you could address this topic against Analyzer ( specifically VTune ) Forum -&nbsp;<A href="https://community.intel.com/t5/Analyzers/bd-p/analyzers" target="_blank">https://community.intel.com/t5/Analyzers/bd-p/analyzers</A></P> <P>&nbsp;</P> Thu, 01 Feb 2024 04:56:26 GMT https://community.intel.com/t5/Intel-Integrated-Performance/L1-dcache-loads-meansing/m-p/1568196#M28621 Gennady_F_Intel 2024-02-01T04:56:26Z