https://community.intel.com/t5/Intel-Integrated-Performance/Memory-bug-related-to-ippsFIRMR-16sc/m-p/1649883#M28938 <P><SPAN class="">I am seeing inconsistent behavior between two versions of the FIRMR function that performs multi rate filtering. The version that works as expected is the ippsFIRMR_32fc function, the version that does not work as expected is ippsFIRMR_16sc.</SPAN><BR /><SPAN class="">Attached is the code used to show this difference. </SPAN><SPAN class="">Note that the fc32 and 16sc versions are practically identical, the parts that differ are highlighted in the `Setup` struct.</SPAN></P><P>&nbsp;</P><P>The attached code can be compiled for the 16sc version by setting the parameter `use_16sc` to true. To compile the 32fc version set the `use_16sc` parameter to false. The 16sc version has a segfault while the 32fc version does not.</P><P>&nbsp;</P><P>There are several things I have noticed that cause the segfault to occur:</P><P>- When the taps_len parameter is greater than or equal to 12 this segfault occurs. For 11 and under there is no segfault.</P><P>- If the second filter call is the exact same as the first then no segfault occurs. The segfault occurs when the role of the source and destination buffers are reversed.</P><P>&nbsp;</P><P>The reason for reversing the buffers is to avoid copying or reallocating space for more buffers. After the first filter call the delay_src buffer serves no use so it should be reusable, such as the delay destination buffer for the second call to filter. After the first filter call the delay destination buffer should have values that are meant to be used as the delay source for the next filtering call.&nbsp; Note in the attached code we are simply using the same input and output buffers for both filter calls which is not realistic for an actual use case. It is done this way to simplify the example code displaying the bug.</P> Mon, 16 Dec 2024 17:11:46 GMT kwadolowski 2024-12-16T17:11:46Z https://community.intel.com/t5/Intel-Integrated-Performance/Memory-bug-related-to-ippsFIRMR-16sc/m-p/1649883#M28938 <P><SPAN class="">I am seeing inconsistent behavior between two versions of the FIRMR function that performs multi rate filtering. The version that works as expected is the ippsFIRMR_32fc function, the version that does not work as expected is ippsFIRMR_16sc.</SPAN><BR /><SPAN class="">Attached is the code used to show this difference. </SPAN><SPAN class="">Note that the fc32 and 16sc versions are practically identical, the parts that differ are highlighted in the `Setup` struct.</SPAN></P><P>&nbsp;</P><P>The attached code can be compiled for the 16sc version by setting the parameter `use_16sc` to true. To compile the 32fc version set the `use_16sc` parameter to false. The 16sc version has a segfault while the 32fc version does not.</P><P>&nbsp;</P><P>There are several things I have noticed that cause the segfault to occur:</P><P>- When the taps_len parameter is greater than or equal to 12 this segfault occurs. For 11 and under there is no segfault.</P><P>- If the second filter call is the exact same as the first then no segfault occurs. The segfault occurs when the role of the source and destination buffers are reversed.</P><P>&nbsp;</P><P>The reason for reversing the buffers is to avoid copying or reallocating space for more buffers. After the first filter call the delay_src buffer serves no use so it should be reusable, such as the delay destination buffer for the second call to filter. After the first filter call the delay destination buffer should have values that are meant to be used as the delay source for the next filtering call.&nbsp; Note in the attached code we are simply using the same input and output buffers for both filter calls which is not realistic for an actual use case. It is done this way to simplify the example code displaying the bug.</P> Mon, 16 Dec 2024 17:11:46 GMT https://community.intel.com/t5/Intel-Integrated-Performance/Memory-bug-related-to-ippsFIRMR-16sc/m-p/1649883#M28938 kwadolowski 2024-12-16T17:11:46Z https://community.intel.com/t5/Intel-Integrated-Performance/Memory-bug-related-to-ippsFIRMR-16sc/m-p/1650638#M28945 <P>Thank you for posting the issue and providing out reproducer. We reproduced it with your sample code. And we will update here with further investigation.</P><BR /> Thu, 19 Dec 2024 03:13:40 GMT https://community.intel.com/t5/Intel-Integrated-Performance/Memory-bug-related-to-ippsFIRMR-16sc/m-p/1650638#M28945 Ruqiu_C_Intel 2024-12-19T03:13:40Z https://community.intel.com/t5/Intel-Integrated-Performance/Memory-bug-related-to-ippsFIRMR-16sc/m-p/1675744#M29045 <P>Thank you for your patience.</P><P>The fix will be available in a future release.</P><BR /> Tue, 18 Mar 2025 04:48:38 GMT https://community.intel.com/t5/Intel-Integrated-Performance/Memory-bug-related-to-ippsFIRMR-16sc/m-p/1675744#M29045 Ruqiu_C_Intel 2025-03-18T04:48:38Z https://community.intel.com/t5/Intel-Integrated-Performance/Memory-bug-related-to-ippsFIRMR-16sc/m-p/1677320#M29048 <P>Thank you for looking into this! I look forward to the next release</P> Mon, 24 Mar 2025 13:07:23 GMT https://community.intel.com/t5/Intel-Integrated-Performance/Memory-bug-related-to-ippsFIRMR-16sc/m-p/1677320#M29048 kwadolowski 2025-03-24T13:07:23Z https://community.intel.com/t5/Intel-Integrated-Performance/Memory-bug-related-to-ippsFIRMR-16sc/m-p/1681530#M29056 <P>Intel IPP 2022.1.0 is available for the fix.</P> <DIV> <DIV id="bodyDisplay" class="lia-message-body lia-component-message-view-widget-body lia-component-body-signature-highlight-escalation lia-component-message-view-widget-body-signature-highlight-escalation section_selectors question_selectors first_st_section" data-section_field_id="b31d-c176-7c6d"> <DIV class="lia-message-body-content sub_section_element_selectors"> <DIV class="col-1 left"> <DIV class="twocolumnpar-one intelparsys"> <DIV class="colorBlock section"> <DIV id="" class="intel-ws link-default theme-white theme-light-default" data-component="colorBlock" data-component-id=""> <DIV class="atom-color-block color-block tile-version"> <DIV class="m-color-block content color-block-color-main has-spark marquee-content spark-none"> <DIV class="ws-a-title atomTitle"> <DIV id="" class="intel-ws link-default " data-component="atomTitle" data-component-id="4">&nbsp;</DIV> </DIV> </DIV> </DIV> </DIV> </DIV> </DIV> </DIV> <DIV class="col-2 left"> <DIV class="twocolumnpar-two intelparsys"> <DIV class="colorBlock section"> <DIV id="" class="intel-ws link-default theme-white theme-light-default" data-component="colorBlock" data-component-id=""> <DIV class="atom-color-block color-block tile-version"> <DIV class="m-color-block content color-block-color-main has-spark marquee-content spark-none"> <DIV class="colorblock-par parsys"> <DIV class="atomCta section"> <DIV class=""><A href="https://community.intel.com/t5/Intel-Integrated-Performance/Intel-Integrated-Performance-Primitives-Intel-IPP-version-2022-1/m-p/1678246#M29049" target="_blank">Intel® Integrated Performance Primitives (Intel® IPP) version 2022.1.0 is released. - Intel Community</A></DIV> </DIV> </DIV> </DIV> </DIV> </DIV> </DIV> </DIV> </DIV> </DIV> </DIV> </DIV> <DIV class="AddMessageTags lia-message-tags lia-component-message-view-widget-tags"><A id="showAddTag" class="lia-link-navigation add-tag-link" role="button" href="https://community.intel.com/t5/Intel-Integrated-Performance/Intel-Integrated-Performance-Primitives-Intel-IPP-version-2022-1/m-p/1678246#" aria-label="Add Tag..." target="_blank">Add tags</A></DIV> Wed, 09 Apr 2025 01:39:55 GMT https://community.intel.com/t5/Intel-Integrated-Performance/Memory-bug-related-to-ippsFIRMR-16sc/m-p/1681530#M29056 Ruqiu_C_Intel 2025-04-09T01:39:55Z