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    <title>topic DivCRev_64f in Intel® Integrated Performance Primitives</title>
    <link>https://community.intel.com/t5/Intel-Integrated-Performance/DivCRev-64f/m-p/819458#M4581</link>
    <description>&lt;P&gt;Unfortunately we can't use the 32f variant. We can work around it fine (invert and then mult by constant), but is there a way to request for it to be included in future versions?&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Ben&lt;/P&gt;</description>
    <pubDate>Wed, 22 Sep 2010 09:21:35 GMT</pubDate>
    <dc:creator>Ben_Young</dc:creator>
    <dc:date>2010-09-22T09:21:35Z</dc:date>
    <item>
      <title>DivCRev_64f</title>
      <link>https://community.intel.com/t5/Intel-Integrated-Performance/DivCRev-64f/m-p/819454#M4577</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I was wondering the best place to ask about omissions/desired functionality in the IPP? We're looking to make use of the IPP in our app, and most of the primitives are covered, but I can't find a DivCRev for double precision vectors. Is there a technical reason this is missing, or does it need someone to ask for it?&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Ben Young&lt;/P&gt;</description>
      <pubDate>Wed, 22 Sep 2010 08:55:11 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Integrated-Performance/DivCRev-64f/m-p/819454#M4577</guid>
      <dc:creator>Ben_Young</dc:creator>
      <dc:date>2010-09-22T08:55:11Z</dc:date>
    </item>
    <item>
      <title>DivCRev_64f</title>
      <link>https://community.intel.com/t5/Intel-Integrated-Performance/DivCRev-64f/m-p/819455#M4578</link>
      <description>&lt;P&gt;Hi Ben,&lt;/P&gt;&lt;P&gt;This is right forum to ask any questions related to IPP.&lt;/P&gt;&lt;P&gt;IPP has got function to Divides a constant value by each element of a  ippsDivCRev.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Please refer &lt;A href="http://software.intel.com/sites/products/documentation/hpc/ipp/pdf/ippsman.pdf"&gt;&lt;SPAN style="text-decoration: underline;"&gt;to IPP signal processing manual&lt;/SPAN&gt;&lt;/A&gt; to get additional information about this function.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Naveen Gv&lt;/P&gt;</description>
      <pubDate>Wed, 22 Sep 2010 09:03:18 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Integrated-Performance/DivCRev-64f/m-p/819455#M4578</guid>
      <dc:creator>Naveen_G_Intel</dc:creator>
      <dc:date>2010-09-22T09:03:18Z</dc:date>
    </item>
    <item>
      <title>DivCRev_64f</title>
      <link>https://community.intel.com/t5/Intel-Integrated-Performance/DivCRev-64f/m-p/819456#M4579</link>
      <description>&lt;P&gt;Hi Naveen,&lt;/P&gt;&lt;P&gt;Thanks for the reply. I have seen ippsDivCRev, but there doesn't appear to be a 64f variant! Is that just a doc omission, or is there really no such method?&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Ben&lt;/P&gt;</description>
      <pubDate>Wed, 22 Sep 2010 09:05:52 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Integrated-Performance/DivCRev-64f/m-p/819456#M4579</guid>
      <dc:creator>Ben_Young</dc:creator>
      <dc:date>2010-09-22T09:05:52Z</dc:date>
    </item>
    <item>
      <title>DivCRev_64f</title>
      <link>https://community.intel.com/t5/Intel-Integrated-Performance/DivCRev-64f/m-p/819457#M4580</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;64f variant is not there, means not implemented in IPP. You can try to use ippsDivCRev_32f.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Naveen Gv&lt;/P&gt;</description>
      <pubDate>Wed, 22 Sep 2010 09:17:57 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Integrated-Performance/DivCRev-64f/m-p/819457#M4580</guid>
      <dc:creator>Naveen_G_Intel</dc:creator>
      <dc:date>2010-09-22T09:17:57Z</dc:date>
    </item>
    <item>
      <title>DivCRev_64f</title>
      <link>https://community.intel.com/t5/Intel-Integrated-Performance/DivCRev-64f/m-p/819458#M4581</link>
      <description>&lt;P&gt;Unfortunately we can't use the 32f variant. We can work around it fine (invert and then mult by constant), but is there a way to request for it to be included in future versions?&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Ben&lt;/P&gt;</description>
      <pubDate>Wed, 22 Sep 2010 09:21:35 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Integrated-Performance/DivCRev-64f/m-p/819458#M4581</guid>
      <dc:creator>Ben_Young</dc:creator>
      <dc:date>2010-09-22T09:21:35Z</dc:date>
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