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    <title>topic ippsFIR_32f  delay Line: delayline behaviour and FIR implementation in Intel® Integrated Performance Primitives</title>
    <link>https://community.intel.com/t5/Intel-Integrated-Performance/ippsFIR-32f-delay-Line-delayline-behaviour-and-FIR/m-p/822799#M4903</link>
    <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I would like to use ippsFIR_32f function for filtering. I have written the following code. &lt;/P&gt;&lt;P&gt;****************************************************&lt;/P&gt;&lt;P&gt;FloatVector pDlyLine(Ntaps);&lt;/P&gt;&lt;P&gt;pDlyLine.assign(Ntaps-1,0);&lt;/P&gt;&lt;P&gt;IppsFIRState_32f *ppState_FIR=NULL;//Pointer which will point to FIR delay line structure&lt;/P&gt;&lt;P&gt;Ipp32f *temp_fir_out_buffer=NULL,*temp_alloc_buff=NULL;&lt;/P&gt;&lt;P&gt;std::copy(pSrc,pSrc+Ntaps/2+IntErr,&amp;amp;pDlyLine[Ntaps/2-1+IntErr]);&lt;/P&gt;&lt;P&gt;ippStats= ippsFIR_32f( pSrc+Ntaps/2+IntErr, temp_fir_out_buffer, Ninput, ppState_FIR&lt;/P&gt;&lt;P&gt;ippStats = ippsFIRInitAlloc_32f( &amp;amp;ppState_FIR, pFilter, Ntaps, &amp;amp;pDlyLine[0])&lt;/P&gt;&lt;P&gt;ippsFIRFree_32f(ppState_FIR);&lt;/P&gt;&lt;P&gt;************************************************************&lt;/P&gt;&lt;P&gt;Here we are setting the first half of delay line with 0 and rest half with initial ntaps/2 src input. While calling the filter we are skipping the first ntaps/2 samples as they are already in delayline, So as per this configuration&lt;/P&gt;&lt;P&gt;we should the get y[0] as the valid out instead of filter ramp. But output is not correct for first ntaps/2 samples. Can anyone tell if something I missed in understanding the delay line in the function? I referred the following post in the forum for this implementation. (http://software.intel.com/file/32933 Difference between FIR MR and FIR MR Stream? &lt;A href="http://software.intel.com/en-us/forums/showthread.php?t=79151)" target="_blank"&gt;http://software.intel.com/en-us/forums/showthread.php?t=79151)&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Kindly provide help with regards to delayline behaviour and FIR implementation&lt;BR /&gt;&lt;BR /&gt;Regards&lt;/P&gt;&lt;P&gt;Rohit&lt;/P&gt;</description>
    <pubDate>Thu, 26 Jan 2012 15:04:01 GMT</pubDate>
    <dc:creator>rohitspandey</dc:creator>
    <dc:date>2012-01-26T15:04:01Z</dc:date>
    <item>
      <title>ippsFIR_32f  delay Line: delayline behaviour and FIR implementation</title>
      <link>https://community.intel.com/t5/Intel-Integrated-Performance/ippsFIR-32f-delay-Line-delayline-behaviour-and-FIR/m-p/822799#M4903</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I would like to use ippsFIR_32f function for filtering. I have written the following code. &lt;/P&gt;&lt;P&gt;****************************************************&lt;/P&gt;&lt;P&gt;FloatVector pDlyLine(Ntaps);&lt;/P&gt;&lt;P&gt;pDlyLine.assign(Ntaps-1,0);&lt;/P&gt;&lt;P&gt;IppsFIRState_32f *ppState_FIR=NULL;//Pointer which will point to FIR delay line structure&lt;/P&gt;&lt;P&gt;Ipp32f *temp_fir_out_buffer=NULL,*temp_alloc_buff=NULL;&lt;/P&gt;&lt;P&gt;std::copy(pSrc,pSrc+Ntaps/2+IntErr,&amp;amp;pDlyLine[Ntaps/2-1+IntErr]);&lt;/P&gt;&lt;P&gt;ippStats= ippsFIR_32f( pSrc+Ntaps/2+IntErr, temp_fir_out_buffer, Ninput, ppState_FIR&lt;/P&gt;&lt;P&gt;ippStats = ippsFIRInitAlloc_32f( &amp;amp;ppState_FIR, pFilter, Ntaps, &amp;amp;pDlyLine[0])&lt;/P&gt;&lt;P&gt;ippsFIRFree_32f(ppState_FIR);&lt;/P&gt;&lt;P&gt;************************************************************&lt;/P&gt;&lt;P&gt;Here we are setting the first half of delay line with 0 and rest half with initial ntaps/2 src input. While calling the filter we are skipping the first ntaps/2 samples as they are already in delayline, So as per this configuration&lt;/P&gt;&lt;P&gt;we should the get y[0] as the valid out instead of filter ramp. But output is not correct for first ntaps/2 samples. Can anyone tell if something I missed in understanding the delay line in the function? I referred the following post in the forum for this implementation. (http://software.intel.com/file/32933 Difference between FIR MR and FIR MR Stream? &lt;A href="http://software.intel.com/en-us/forums/showthread.php?t=79151)" target="_blank"&gt;http://software.intel.com/en-us/forums/showthread.php?t=79151)&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Kindly provide help with regards to delayline behaviour and FIR implementation&lt;BR /&gt;&lt;BR /&gt;Regards&lt;/P&gt;&lt;P&gt;Rohit&lt;/P&gt;</description>
      <pubDate>Thu, 26 Jan 2012 15:04:01 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Integrated-Performance/ippsFIR-32f-delay-Line-delayline-behaviour-and-FIR/m-p/822799#M4903</guid>
      <dc:creator>rohitspandey</dc:creator>
      <dc:date>2012-01-26T15:04:01Z</dc:date>
    </item>
    <item>
      <title>ippsFIR_32f  delay Line: delayline behaviour and FIR implementa</title>
      <link>https://community.intel.com/t5/Intel-Integrated-Performance/ippsFIR-32f-delay-Line-delayline-behaviour-and-FIR/m-p/822800#M4904</link>
      <description>Rohit,&lt;BR /&gt;&lt;BR /&gt;Have you taken a look at the IPP FIR sample (fir.cpp)available in &lt;A href="http://software.intel.com/en-us/articles/intel-integrated-performance-primitives-intel-ipp-intel-ipp-source-code-examples/"&gt;http://software.intel.com/en-us/articles/intel-integrated-performance-primitives-intel-ipp-intel-ipp-source-code-examples/&lt;/A&gt; ?&lt;BR /&gt;&lt;BR /&gt;-Vipin&lt;BR /&gt;&lt;BR /&gt;</description>
      <pubDate>Thu, 26 Jan 2012 15:29:44 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Integrated-Performance/ippsFIR-32f-delay-Line-delayline-behaviour-and-FIR/m-p/822800#M4904</guid>
      <dc:creator>VipinKumar_E_Intel</dc:creator>
      <dc:date>2012-01-26T15:29:44Z</dc:date>
    </item>
    <item>
      <title>ippsFIR_32f  delay Line: delayline behaviour and FIR implementa</title>
      <link>https://community.intel.com/t5/Intel-Integrated-Performance/ippsFIR-32f-delay-Line-delayline-behaviour-and-FIR/m-p/822801#M4905</link>
      <description>Hi,&lt;BR /&gt;I checked the fir.cpp. and Resample.cpp in both the case the delayline is set to 0. I am interested in case where I utilise the delayline to be loaded with the input samples i.e the filter output doesn't have filter ramp. as given in link &lt;A href="http://software.intel.com/file/32933"&gt;http://software.intel.com/file/32933&lt;/A&gt;. &lt;BR /&gt;&lt;BR /&gt;So ideally the &lt;BR /&gt;&lt;BR /&gt;At start the filter input struct should look like this &lt;BR /&gt;&lt;BR /&gt;Inputlength = N;&lt;BR /&gt;&lt;BR /&gt;dlyLn =x0 x1 x2 x3..... xfilt_len-1&lt;BR /&gt;Input = xFilt_len,xFilt_len+1,.......xN&lt;BR /&gt;filterCoff = h1,h2,h3......hfilt_Len&lt;BR /&gt;&lt;BR /&gt;y[0] = x0*h1+x1*h2+.....+xFilt_len-1*hFilt_len;&lt;BR /&gt;y[1] = x1*h1+..............+xFilt_len*hFilt_len;&lt;BR /&gt;...&lt;BR /&gt;...&lt;BR /&gt;&lt;BR /&gt;y[N-filt_len]=xN-filt_Len*h1+.......xN*hFilt_len&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;Can you is it possible to achive the above by setting the delay line, the way i mentioned. Or Can you explain how the input and delayline being utilised in the ippsFIR_32f?&lt;BR /&gt;&lt;BR /&gt;Regards&lt;BR /&gt;Rohit</description>
      <pubDate>Thu, 26 Jan 2012 16:01:55 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Integrated-Performance/ippsFIR-32f-delay-Line-delayline-behaviour-and-FIR/m-p/822801#M4905</guid>
      <dc:creator>rohitspandey</dc:creator>
      <dc:date>2012-01-26T16:01:55Z</dc:date>
    </item>
    <item>
      <title>ippsFIR_32f  delay Line: delayline behaviour and FIR implementa</title>
      <link>https://community.intel.com/t5/Intel-Integrated-Performance/ippsFIR-32f-delay-Line-delayline-behaviour-and-FIR/m-p/822802#M4906</link>
      <description>Hi,&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;I figured out. The delay line is setup with the pointer pointing to the D[Ntaps] instead on D[0]. So to load the delay line I have to reverse the input instead pointing to the x[0].So when i reverse it works fine&lt;BR /&gt;&lt;BR /&gt;Regards&lt;BR /&gt;Rohit</description>
      <pubDate>Fri, 27 Jan 2012 16:29:43 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Integrated-Performance/ippsFIR-32f-delay-Line-delayline-behaviour-and-FIR/m-p/822802#M4906</guid>
      <dc:creator>rohitspandey</dc:creator>
      <dc:date>2012-01-27T16:29:43Z</dc:date>
    </item>
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