<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Evaluating DMIP in Intel® Integrated Performance Primitives</title>
    <link>https://community.intel.com/t5/Intel-Integrated-Performance/Evaluating-DMIP/m-p/870987#M8926</link>
    <description>Hi all,&lt;BR /&gt;&lt;BR /&gt;I am working on vision algorithms, using IPP 5.3 so far, and now we start evaluating IPP 6.0, to try and squeeze some additional perf boost using the new DMIP.&lt;BR /&gt;&lt;BR /&gt;Well, I have played with it a bit, by simply implementing a simple edge detection algorithm based on Sobel.&lt;BR /&gt;I compared the new DMIP implementation perf to the "standard" IPP implementation perf when computing edges of relatively large matrix (11MB). Indeed a perf boost of ~ X3 was achieved on a Core2 Duo T7300@2GHz CPU. Impressive.&lt;BR /&gt;&lt;BR /&gt;&lt;STRONG&gt;But 2 things still bother me:&lt;/STRONG&gt;&lt;BR /&gt;1. It appears that although the IPP-implementation uses ~90% CPU, the DMIP-implementation uses ~50% - suggesting that DMIP is only utilizing a single core. &lt;EM&gt;Any comments???&lt;/EM&gt;&lt;BR /&gt;2. I would like to see if indeed the perf boost in caused due to CPU cache fault reduction in the DMIP (the whole idea behind DMIP). &lt;EM&gt;How can I validate this on Win platform?&lt;/EM&gt;&lt;BR /&gt;&lt;BR /&gt;Cheers&lt;BR /&gt;Hagay</description>
    <pubDate>Thu, 08 Jan 2009 09:41:19 GMT</pubDate>
    <dc:creator>hagay_lupeskoinscan-</dc:creator>
    <dc:date>2009-01-08T09:41:19Z</dc:date>
    <item>
      <title>Evaluating DMIP</title>
      <link>https://community.intel.com/t5/Intel-Integrated-Performance/Evaluating-DMIP/m-p/870987#M8926</link>
      <description>Hi all,&lt;BR /&gt;&lt;BR /&gt;I am working on vision algorithms, using IPP 5.3 so far, and now we start evaluating IPP 6.0, to try and squeeze some additional perf boost using the new DMIP.&lt;BR /&gt;&lt;BR /&gt;Well, I have played with it a bit, by simply implementing a simple edge detection algorithm based on Sobel.&lt;BR /&gt;I compared the new DMIP implementation perf to the "standard" IPP implementation perf when computing edges of relatively large matrix (11MB). Indeed a perf boost of ~ X3 was achieved on a Core2 Duo T7300@2GHz CPU. Impressive.&lt;BR /&gt;&lt;BR /&gt;&lt;STRONG&gt;But 2 things still bother me:&lt;/STRONG&gt;&lt;BR /&gt;1. It appears that although the IPP-implementation uses ~90% CPU, the DMIP-implementation uses ~50% - suggesting that DMIP is only utilizing a single core. &lt;EM&gt;Any comments???&lt;/EM&gt;&lt;BR /&gt;2. I would like to see if indeed the perf boost in caused due to CPU cache fault reduction in the DMIP (the whole idea behind DMIP). &lt;EM&gt;How can I validate this on Win platform?&lt;/EM&gt;&lt;BR /&gt;&lt;BR /&gt;Cheers&lt;BR /&gt;Hagay</description>
      <pubDate>Thu, 08 Jan 2009 09:41:19 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Integrated-Performance/Evaluating-DMIP/m-p/870987#M8926</guid>
      <dc:creator>hagay_lupeskoinscan-</dc:creator>
      <dc:date>2009-01-08T09:41:19Z</dc:date>
    </item>
    <item>
      <title>Re: Evaluating DMIP</title>
      <link>https://community.intel.com/t5/Intel-Integrated-Performance/Evaluating-DMIP/m-p/870988#M8927</link>
      <description>&lt;DIV style="margin:0px;"&gt;&lt;/DIV&gt;
&lt;BR /&gt;Could you please provide your test case for us to investigate 50% cpu usage ussue?&lt;BR /&gt;&lt;BR /&gt;You may use VTune to measure an average cache misses count to see the DMIP advantages&lt;BR /&gt;&lt;BR /&gt;Regards,&lt;BR /&gt; Vladimir</description>
      <pubDate>Sun, 11 Jan 2009 08:53:39 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Integrated-Performance/Evaluating-DMIP/m-p/870988#M8927</guid>
      <dc:creator>Vladimir_Dudnik</dc:creator>
      <dc:date>2009-01-11T08:53:39Z</dc:date>
    </item>
    <item>
      <title>Re: Evaluating DMIP</title>
      <link>https://community.intel.com/t5/Intel-Integrated-Performance/Evaluating-DMIP/m-p/870989#M8928</link>
      <description>Hi Vladimir,&lt;BR /&gt;&lt;BR /&gt;Thanks for the response.&lt;BR /&gt;The code snippet is below, please note: (1) It is in C++/CLI (2) The input and output matrices are allocated on managed heap (3) The Matrix generic datatype is a T one-dimensional array (4) The code works as expected&lt;BR /&gt;&lt;BR /&gt;About VTunes - thanks, I'll check it.&lt;BR /&gt;&lt;BR /&gt;Hagay&lt;BR /&gt;&lt;BR /&gt;Code snippet:&lt;BR /&gt;
&lt;PRE&gt;[cpp]Matrix&lt;BYTE&gt; ^EdgeDetectDmip::DetectEdges(Matrix&lt;BYTE&gt; ^input)
{
	Matrix&lt;BYTE&gt;^ output = gcnew Matrix&lt;BYTE&gt;(input-&amp;gt;Size);

	IppiSize roi = {input-&amp;gt;Size.Width, input-&amp;gt;Size.Height};
	pin_ptr&lt;BYTE&gt; inData = &amp;amp;(input-&amp;gt;GetBuffer()[0]);
	pin_ptr&lt;BYTE&gt; outData = &amp;amp;(output-&amp;gt;GetBuffer()[0]);

	IppDataType dataType = ipp8u;
	IppChannels channels = ippC1;

	Image A(inData, dataType, channels, roi, roi.width);
	Image D(outData, dataType, channels, roi, roi.width);
	Kernel KH(idmFilterSobelHoriz);
	Kernel KV(idmFilterSobelVert);
	
	Graph O;
	O=To32f(A);
	D=MaxVal(To8u(Sqrt(Sqr(O*KH)+Sqr(O*KV))), 150, 0);

	return output;
}[/cpp]&lt;/BYTE&gt;&lt;/BYTE&gt;&lt;/BYTE&gt;&lt;/BYTE&gt;&lt;/BYTE&gt;&lt;/BYTE&gt;&lt;/PRE&gt;
&lt;BR /&gt;</description>
      <pubDate>Sun, 11 Jan 2009 17:02:42 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Integrated-Performance/Evaluating-DMIP/m-p/870989#M8928</guid>
      <dc:creator>hagay_lupeskoinscan-</dc:creator>
      <dc:date>2009-01-11T17:02:42Z</dc:date>
    </item>
    <item>
      <title>Re: Evaluating DMIP</title>
      <link>https://community.intel.com/t5/Intel-Integrated-Performance/Evaluating-DMIP/m-p/870990#M8929</link>
      <description>&lt;DIV style="margin:0px;"&gt;
&lt;DIV id="quote_reply" style="width: 100%; margin-top: 5px;"&gt;
&lt;DIV style="margin-left:2px;margin-right:2px;"&gt;Quoting - &lt;A href="https://community.intel.com/en-us/profile/61463"&gt;Vladimir Dudnik&lt;/A&gt;&lt;/DIV&gt;
&lt;DIV style="background-color:#E5E5E5; padding:5px;border: 1px; border-style: inset;margin-left:2px;margin-right:2px;"&gt;&lt;EM&gt; &lt;BR /&gt;Could you please provide your test case for us to investigate 50% cpu usage ussue?&lt;BR /&gt;&lt;BR /&gt;You may use VTune to measure an average cache misses count to see the DMIP advantages&lt;BR /&gt;&lt;BR /&gt;Regards,&lt;BR /&gt; Vladimir&lt;/EM&gt;&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;BR /&gt;Hi Vladimir,&lt;BR /&gt;&lt;BR /&gt;I have supplied the code snippet, could you please go over it and update me?&lt;BR /&gt;Also, it appears the problem is in some OMP failure.&lt;BR /&gt;&lt;BR /&gt;Running the following code, it appears that DMIP can not use OMP for some reason:&lt;BR /&gt;int i = Control::GetMaxNumThread(); // i get the value 1, although this is a dual core CPU&lt;BR /&gt;DMIP::idmStatus stat = Control::SetNumThread(2); // stat is -4, meaning OMP error&lt;BR /&gt;&lt;BR /&gt;However, IPP is using the two cores without a problem:&lt;BR /&gt;int cores = ippGetNumCoresOnDie(); // returns 2&lt;BR /&gt; int numThreads;&lt;BR /&gt; IppStatus status1 = ippGetNumThreads(&amp;amp;numThreads); // returns 2&lt;BR /&gt;&lt;BR /&gt;Any explanations/solutions?&lt;BR /&gt;&lt;BR /&gt;Thanks, Hagay&lt;BR /&gt;</description>
      <pubDate>Thu, 15 Jan 2009 05:38:00 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Integrated-Performance/Evaluating-DMIP/m-p/870990#M8929</guid>
      <dc:creator>hagay_lupeskoinscan-</dc:creator>
      <dc:date>2009-01-15T05:38:00Z</dc:date>
    </item>
    <item>
      <title>Re: Evaluating DMIP</title>
      <link>https://community.intel.com/t5/Intel-Integrated-Performance/Evaluating-DMIP/m-p/870991#M8930</link>
      <description>&lt;DIV style="margin:0px;"&gt;&lt;/DIV&gt;
Hi Hagay,&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;we've found issue in IPP 6.0 DMIP DLL which do not allow to set number of threads more than 1. This will be fixed in the next version. Please submit bug report to &lt;A href="https://community.intel.com/premier.intel.com"&gt;Intel Premier Support&lt;/A&gt;, so you will be notified when solution will be ready.&lt;BR /&gt;&lt;BR /&gt;Regards,&lt;BR /&gt; Vladimir&lt;BR /&gt;</description>
      <pubDate>Thu, 15 Jan 2009 14:33:13 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Integrated-Performance/Evaluating-DMIP/m-p/870991#M8930</guid>
      <dc:creator>Vladimir_Dudnik</dc:creator>
      <dc:date>2009-01-15T14:33:13Z</dc:date>
    </item>
  </channel>
</rss>

