topic Small mess up with Sandy Bridge? in Intel® ISA Extensions

Small mess up with Sandy Bridge?

davidc1 — Wed, 26 Jan 2011 10:13:36 GMT

On the Intel IDF Fall 2010 San Franscisco presentation titled Intel Next Generation Microarchitecture Codename Sandy Bridge: New Processor Innovations, it clearly states that ADC throughput was doubled compared to previous generation processors:

"ADC(Add with Carry) throughput doubled"

These two results show the opposite, the ADC throughput is halved compared to Clarkdale.

Clarkdale: http://www.freeweb.hu/instlatx64/GenuineIntel0020652_Clarkdale_InstLatX64.txt
Sandy Bridge: http://www.freeweb.hu/instlatx64/GenuineIntel00206A7_SandyBridge_InstLatX64.txt

So what happened guys? The only explanation I could come up is something screwed up since then and launch.

Add to that:
-No proper 23.976 support in the 6 series chipsets
-Increased L2 cache latency
-Increased instruction latency
-Messy Linux support and drivers
-Poor OpenGL support in both Linux and Windows

On the Anandtech article, they mention the reason they couldn't fit 23.976 support on the 6 series chipsets is because they had to comply with the Tick Tock schedule. The CPU is no doubt still impressive, but it seems along the way, you guys screwed up.

Small mess up with Sandy Bridge?

maratyszcza — Sat, 05 Feb 2011 23:53:41 GMT

The Everest dumps you refer to actually indicate not usual throughput (how many independent instructions can be executed in 1 clock cycle), but Reciprocal Throughput (how many clock does it take to execute an instruction in a stream of independent instructions). Consequently, as Sandy Bridge has Reciprocal Throughtput for ADC reduced from 2 clocks to 1, it can execute ADC every clock cycle, while Nehalem could only execute ADC every other clock.

Small mess up with Sandy Bridge?

capens__nicolas — Mon, 07 Feb 2011 07:11:44 GMT

Quoting davidc1

-Increased L2 cache latency
-Increased instruction latency

That's hardly relevant. You have to look at the whole picture. Sandy Bridge is significantly faster and power efficient.

Note that L3 cache latency went down considerably. Increasing L2 cache latency by a bit must have been a compromise which resulted in a better balance between all of the parameters. Increasing the instruction latency probably allowed them to use relatively slower but more power efficient transistors. Overall it's still a win on all fronts.

Let me put it this way: If a racecar became faster by replacing the engine with a much lighter one with slightly less power, would you consider that "screwing up"? Only external parameters matter in the end.

Small mess up with Sandy Bridge?

davidc1 — Fri, 11 Feb 2011 00:26:37 GMT

You are right about this one, I got them confused. I still don't think many will disagree it wasn't the most smoothest launch though.