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    <title>topic MP (multi-processor) system - LAPIC query in Intel® ISA Extensions</title>
    <link>https://community.intel.com/t5/Intel-ISA-Extensions/MP-multi-processor-system-LAPIC-query/m-p/826702#M1612</link>
    <description>Continuing what Shih Kuo wrote, vol 3 also says the following:&lt;BR /&gt;The Pentium 4, Intel Xeon, and P6 family processors permit the starting address of&lt;BR /&gt;the APIC registers to be relocated from FEE00000H to another physical address by&lt;BR /&gt;modifying the value in the 24-bit base address field of the IA32_APIC_BASE MSR.&lt;BR /&gt;This extension of the APIC architecture is provided to help resolve conflicts with&lt;BR /&gt;memory maps of existing systems and to allow individual processors in an MP system&lt;BR /&gt;to map their APIC registers to different locations in physical memory.&lt;BR /&gt;&lt;BR /&gt;[ This is MSR 01Bh. ]&lt;BR /&gt;&lt;BR /&gt;Are you sure you want to change the base address for the Local APIC of your APs?&lt;BR /&gt;The Local APIC address space is private to each processor, so (as far as I know)&lt;BR /&gt;one processor can not modify the Local APIC registers of another processor.&lt;BR /&gt;&lt;BR /&gt;Typicaly a BIOS would start up each AP, one at a time, with a SIPI to configure the&lt;BR /&gt;SMM base address. The Local APIC address could be modified at the same time.&lt;BR /&gt;</description>
    <pubDate>Sat, 21 May 2011 06:39:25 GMT</pubDate>
    <dc:creator>Chris_Hooper</dc:creator>
    <dc:date>2011-05-21T06:39:25Z</dc:date>
    <item>
      <title>MP (multi-processor) system - LAPIC query</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/MP-multi-processor-system-LAPIC-query/m-p/826700#M1610</link>
      <description>Hi all,&lt;BR /&gt;&lt;BR /&gt;This is my first post and I don't know if this is the right newsgroup for the question I have. I am a newbie and reading Intel Software Development manual for my own knowledge purposes. I am confused with Local APIC and it's base memory address in multi-processorenvironment. &lt;BR /&gt;&lt;BR /&gt;Each logical/physical CPU has it's own LAPIC, and documentation states that base address for LAPIC are not shareable amongst multiple processors/CPU's. The base address for LAPIC is 0xFFF00000h as per documentation. That's true for BSP. I am confused how to locate LAPIC base address for other (AP) CPU's?&lt;BR /&gt;&lt;BR /&gt;Your help will be appreciated. &lt;BR /&gt;&lt;BR /&gt;Regards&lt;BR /&gt;Gupta</description>
      <pubDate>Tue, 11 Jan 2011 03:04:12 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/MP-multi-processor-system-LAPIC-query/m-p/826700#M1610</guid>
      <dc:creator>mguptamel</dc:creator>
      <dc:date>2011-01-11T03:04:12Z</dc:date>
    </item>
    <item>
      <title>MP (multi-processor) system - LAPIC query</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/MP-multi-processor-system-LAPIC-query/m-p/826701#M1611</link>
      <description>Hi &lt;BR /&gt;I see section 10.4.1 has the following&lt;BR /&gt;&lt;BR /&gt;&lt;P&gt;In MP system configurations, the APIC registers for Intel 64 or IA-32 processors on the system bus are initially mapped to the same 4-KByte region of the physical address space. Software has the option of changing initial mapping to a different 4-KByte region for all the local APICs or of mapping the APIC registers for each local APIC to its own 4-KByte region.&lt;BR /&gt;&lt;BR /&gt;Perhap you saw something different? Can you point to the relevant section?&lt;BR /&gt;Thx&lt;/P&gt;</description>
      <pubDate>Wed, 19 Jan 2011 23:12:56 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/MP-multi-processor-system-LAPIC-query/m-p/826701#M1611</guid>
      <dc:creator>SHIH_K_Intel</dc:creator>
      <dc:date>2011-01-19T23:12:56Z</dc:date>
    </item>
    <item>
      <title>MP (multi-processor) system - LAPIC query</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/MP-multi-processor-system-LAPIC-query/m-p/826702#M1612</link>
      <description>Continuing what Shih Kuo wrote, vol 3 also says the following:&lt;BR /&gt;The Pentium 4, Intel Xeon, and P6 family processors permit the starting address of&lt;BR /&gt;the APIC registers to be relocated from FEE00000H to another physical address by&lt;BR /&gt;modifying the value in the 24-bit base address field of the IA32_APIC_BASE MSR.&lt;BR /&gt;This extension of the APIC architecture is provided to help resolve conflicts with&lt;BR /&gt;memory maps of existing systems and to allow individual processors in an MP system&lt;BR /&gt;to map their APIC registers to different locations in physical memory.&lt;BR /&gt;&lt;BR /&gt;[ This is MSR 01Bh. ]&lt;BR /&gt;&lt;BR /&gt;Are you sure you want to change the base address for the Local APIC of your APs?&lt;BR /&gt;The Local APIC address space is private to each processor, so (as far as I know)&lt;BR /&gt;one processor can not modify the Local APIC registers of another processor.&lt;BR /&gt;&lt;BR /&gt;Typicaly a BIOS would start up each AP, one at a time, with a SIPI to configure the&lt;BR /&gt;SMM base address. The Local APIC address could be modified at the same time.&lt;BR /&gt;</description>
      <pubDate>Sat, 21 May 2011 06:39:25 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/MP-multi-processor-system-LAPIC-query/m-p/826702#M1612</guid>
      <dc:creator>Chris_Hooper</dc:creator>
      <dc:date>2011-05-21T06:39:25Z</dc:date>
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