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    <title>topic Re: Instruction set latency in Intel® ISA Extensions</title>
    <link>https://community.intel.com/t5/Intel-ISA-Extensions/Instruction-set-latency/m-p/857301#M2123</link>
    <description>&lt;DIV style="margin:0px;"&gt;
&lt;DIV id="quote_reply" style="margin-top: 5px; width: 100%;"&gt;
&lt;DIV style="margin-left:2px;margin-right:2px;"&gt;Quoting - &lt;A href="https://community.intel.com/en-us/profile/424190"&gt;sebitab&lt;/A&gt;&lt;/DIV&gt;
&lt;DIV style="background-color:#E5E5E5; padding:5px;border: 1px; border-style: inset;margin-left:2px;margin-right:2px;"&gt;&lt;EM&gt;Hello, I am working on assembly code optimization, I already read the code optimization manual, but I am interested in a list with the instruction set latencies. I search the intel site but I could not find it.
&lt;DIV&gt;Where can I found this?.&lt;/DIV&gt;
&lt;DIV&gt;&lt;BR /&gt;&lt;/DIV&gt;
&lt;DIV&gt;Thanks for your answers.&lt;/DIV&gt;
&lt;/EM&gt;&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;
You can use instruction latencies only for very rough approximation of real number of cycles taken, because actual results depends on whetevera operands are loaded to cache, other instructions in pipeline (conditions) and so on....&lt;BR /&gt;</description>
    <pubDate>Wed, 29 Apr 2009 20:19:44 GMT</pubDate>
    <dc:creator>jancino</dc:creator>
    <dc:date>2009-04-29T20:19:44Z</dc:date>
    <item>
      <title>Instruction set latency</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/Instruction-set-latency/m-p/857299#M2121</link>
      <description>Hello, I am working on assembly code optimization, I already read the code optimization manual, but I am interested in a list with the instruction set latencies. I search the intel site but I could not find it.
&lt;DIV&gt;Where can I found this?.&lt;/DIV&gt;
&lt;DIV&gt;&lt;BR /&gt;&lt;/DIV&gt;
&lt;DIV&gt;Thanks for your answers.&lt;/DIV&gt;</description>
      <pubDate>Thu, 16 Apr 2009 21:51:43 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/Instruction-set-latency/m-p/857299#M2121</guid>
      <dc:creator>sebitab</dc:creator>
      <dc:date>2009-04-16T21:51:43Z</dc:date>
    </item>
    <item>
      <title>Re: Instruction set latency</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/Instruction-set-latency/m-p/857300#M2122</link>
      <description>&lt;DIV style="margin:0px;"&gt;
&lt;DIV id="quote_reply" style="margin-top: 5px; width: 100%;"&gt;
&lt;DIV style="margin-left:2px;margin-right:2px;"&gt;Quoting - &lt;A href="https://community.intel.com/en-us/profile/424190"&gt;sebitab&lt;/A&gt;&lt;/DIV&gt;
&lt;DIV style="background-color:#E5E5E5; padding:5px;border: 1px; border-style: inset;margin-left:2px;margin-right:2px;"&gt;&lt;EM&gt;Hello, I am working on assembly code optimization, I already read the code optimization manual, but I am interested in a list with the instruction set latencies. I search the intel site but I could not find it.
&lt;DIV&gt;Where can I found this?.&lt;/DIV&gt;
&lt;DIV&gt;&lt;BR /&gt;&lt;/DIV&gt;
&lt;DIV&gt;Thanks for your answers.&lt;/DIV&gt;
&lt;/EM&gt;&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;BR /&gt;The latencies are listed in Appendix C of the "Intel 64 and IA-32 Architectures Optimization Reference Manual", which can be downloaded &lt;A href="http://www.intel.com/products/processor/manuals/" target="_self"&gt;here&lt;/A&gt;.&lt;BR /&gt;&lt;BR /&gt;Kind regards&lt;BR /&gt;Thomas</description>
      <pubDate>Fri, 17 Apr 2009 19:17:10 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/Instruction-set-latency/m-p/857300#M2122</guid>
      <dc:creator>Thomas_W_Intel</dc:creator>
      <dc:date>2009-04-17T19:17:10Z</dc:date>
    </item>
    <item>
      <title>Re: Instruction set latency</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/Instruction-set-latency/m-p/857301#M2123</link>
      <description>&lt;DIV style="margin:0px;"&gt;
&lt;DIV id="quote_reply" style="margin-top: 5px; width: 100%;"&gt;
&lt;DIV style="margin-left:2px;margin-right:2px;"&gt;Quoting - &lt;A href="https://community.intel.com/en-us/profile/424190"&gt;sebitab&lt;/A&gt;&lt;/DIV&gt;
&lt;DIV style="background-color:#E5E5E5; padding:5px;border: 1px; border-style: inset;margin-left:2px;margin-right:2px;"&gt;&lt;EM&gt;Hello, I am working on assembly code optimization, I already read the code optimization manual, but I am interested in a list with the instruction set latencies. I search the intel site but I could not find it.
&lt;DIV&gt;Where can I found this?.&lt;/DIV&gt;
&lt;DIV&gt;&lt;BR /&gt;&lt;/DIV&gt;
&lt;DIV&gt;Thanks for your answers.&lt;/DIV&gt;
&lt;/EM&gt;&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;
You can use instruction latencies only for very rough approximation of real number of cycles taken, because actual results depends on whetevera operands are loaded to cache, other instructions in pipeline (conditions) and so on....&lt;BR /&gt;</description>
      <pubDate>Wed, 29 Apr 2009 20:19:44 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/Instruction-set-latency/m-p/857301#M2123</guid>
      <dc:creator>jancino</dc:creator>
      <dc:date>2009-04-29T20:19:44Z</dc:date>
    </item>
    <item>
      <title>Re: Instruction set latency</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/Instruction-set-latency/m-p/857302#M2124</link>
      <description>&lt;DIV&gt;&lt;/DIV&gt;
I find the instruction tables found here: &lt;A href="http://www.agner.org/optimize/"&gt;http://www.agner.org/optimize/&lt;/A&gt; to be very helpful. They are not perfect but they provide a pretty good estimate. &lt;BR /&gt;</description>
      <pubDate>Mon, 12 Oct 2009 11:47:02 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/Instruction-set-latency/m-p/857302#M2124</guid>
      <dc:creator>craigj0</dc:creator>
      <dc:date>2009-10-12T11:47:02Z</dc:date>
    </item>
    <item>
      <title>Re: Instruction set latency</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/Instruction-set-latency/m-p/857303#M2125</link>
      <description>&lt;DIV style="margin:0px;"&gt;
&lt;DIV id="quote_reply" style="width: 100%; margin-top: 5px;"&gt;
&lt;DIV style="margin-left:2px;margin-right:2px;"&gt;Quoting - &lt;A href="https://community.intel.com/en-us/profile/447122"&gt;craigj0&lt;/A&gt;&lt;/DIV&gt;
&lt;DIV style="background-color:#E5E5E5; padding:5px;border: 1px; border-style: inset;margin-left:2px;margin-right:2px;"&gt;&lt;EM&gt; I find the instruction tables found here: &lt;A href="http://www.agner.org/optimize/"&gt;http://www.agner.org/optimize/&lt;/A&gt; to be very helpful. They are not perfect but they provide a pretty good estimate. &lt;BR /&gt;&lt;/EM&gt;&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;BR /&gt;You can also try using Intel Architecture Code Analyzer available on:&lt;BR /&gt;&lt;A href="http://software.intel.com/en-us/articles/intel-architecture-code-analyzer/" target="_blank"&gt;http://software.intel.com/en-us/articles/intel-architecture-code-analyzer/&lt;/A&gt;&lt;BR /&gt;&lt;BR /&gt;It can help you find the dependency chains in your code.&lt;BR /&gt;&lt;BR /&gt;Tal &lt;BR /&gt;</description>
      <pubDate>Thu, 22 Oct 2009 08:40:46 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/Instruction-set-latency/m-p/857303#M2125</guid>
      <dc:creator>Tal_U_Intel</dc:creator>
      <dc:date>2009-10-22T08:40:46Z</dc:date>
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