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    <title>topic Variability in timing measure using RDTSC in Intel® ISA Extensions</title>
    <link>https://community.intel.com/t5/Intel-ISA-Extensions/Variability-in-timing-measure-using-RDTSC/m-p/779212#M239</link>
    <description>Hi,&lt;BR /&gt;&lt;BR /&gt;It's a good question.&lt;BR /&gt;Firsrly, I like your code to set CPU mask and lock pages. But instead of&lt;BR /&gt; sched_setaffinity(0,1,&amp;amp;set);&lt;BR /&gt;there should be more correct to use&lt;BR /&gt; sched_setaffinity(0,&lt;B&gt;sizeof(set)&lt;/B&gt;,&amp;amp;set);&lt;BR /&gt;&lt;BR /&gt;As to instability on the first measurements, they are in my opinion, due to CPU instruction caches or pipe-line init.&lt;BR /&gt;But in general your code is run in OS environment and can be interupted by other devices/demons like timer, IO*, eth0* etc. Look at /proc/interrupts on Linux to see CPU-interupts.&lt;BR /&gt;So fluctuations in time-stamp-counters are possible on the same piece of code.&lt;BR /&gt;Therefore, I'd suggest using kind of statistical analisys of resuts to get predictable performance.&lt;BR /&gt;&lt;BR /&gt;For example, I got the following on my machine:&lt;BR /&gt;t2=4711&lt;BR /&gt;t2=4683&lt;BR /&gt;t2=4683&lt;BR /&gt;t2=4683&lt;BR /&gt;t2=4683&lt;BR /&gt;t2=4683&lt;BR /&gt;t2=4683&lt;BR /&gt;t2=4683&lt;BR /&gt;t2=18123&lt;BR /&gt;t2=4683&lt;BR /&gt;t2=4683&lt;BR /&gt;t2=4683&lt;BR /&gt;t2=4683&lt;BR /&gt;t2=4676&lt;BR /&gt;t2=4683&lt;BR /&gt;t2=4676&lt;BR /&gt;t2=4683&lt;BR /&gt;t2=4683&lt;BR /&gt;t2=4683&lt;BR /&gt;t2=4683&lt;BR /&gt;&lt;BR /&gt;</description>
    <pubDate>Tue, 27 Jul 2010 09:09:52 GMT</pubDate>
    <dc:creator>barragan_villanueva_</dc:creator>
    <dc:date>2010-07-27T09:09:52Z</dc:date>
    <item>
      <title>Variability in timing measure using RDTSC</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/Variability-in-timing-measure-using-RDTSC/m-p/779211#M238</link>
      <description>I'm trying to measure the execution time bound of an inline assembly code, &lt;BR /&gt;using cpuid (for serializing) + rdtsc.&lt;BR /&gt;&lt;BR /&gt;The code measure is a bare assembly loop which is doing only "mov $0x3,%%eax"&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;void * exemple_MOV_im(){&lt;BR /&gt;&lt;BR /&gt; int i;&lt;BR /&gt; int r = 5; &lt;BR /&gt; int* pr = &amp;amp;r;&lt;BR /&gt; timeEx2=0;&lt;BR /&gt;&lt;BR /&gt; asm volatile ("xorl %%eax,%%eax\\n\\t" &lt;BR /&gt; "cpuid\\n\\t"&lt;BR /&gt; "rdtsc\\n\\t"&lt;BR /&gt; "mov %%eax,%%esi\\n\\t"&lt;BR /&gt; "mov $0x0,%%ebx\\n\\t" /* loop counter */&lt;BR /&gt;   "DEB: mov $0x3,%%eax\\n\\t" &lt;BR /&gt; "add $0x1,%%ebx\\n\\t"&lt;BR /&gt; "cmp $0x500,%%ebx\\n\\t"&lt;BR /&gt;   "jle DEB;\\n\\t"&lt;BR /&gt;   "xorl %%eax,%%eax\\n\\t" &lt;BR /&gt; "cpuid\\n\\t"&lt;BR /&gt; "rdtsc\\n\\t"&lt;BR /&gt;   "subl %%esi, %%eax\\n\\t"&lt;BR /&gt;    "mov %%eax, %[t2]\\n\\t"&lt;BR /&gt;   : [t2] "=m" (timeEx2)&lt;BR /&gt;   : &lt;BR /&gt;   : "eax", "ebx" , "ecx", "edx", "esi");&lt;BR /&gt;&lt;BR /&gt; printf("t2=%lu\\n",timeEx2);&lt;BR /&gt;}&lt;BR /&gt;&lt;BR /&gt;int main(){ &lt;BR /&gt;&lt;BR /&gt; cpu_set_t set;&lt;BR /&gt; CPU_ZERO(&amp;amp;set);&lt;BR /&gt; CPU_SET(1,&amp;amp;set);&lt;BR /&gt;&lt;BR /&gt; /* Declaration of a value to check the functions */&lt;BR /&gt; int retcode ;&lt;BR /&gt;&lt;BR /&gt; /* Scheduling parameters */&lt;BR /&gt; int priomax ;&lt;BR /&gt; struct sched_param param;&lt;BR /&gt;&lt;BR /&gt; retcode = mlockall(MCL_CURRENT | MCL_FUTURE);&lt;BR /&gt; if (retcode == -1) {&lt;BR /&gt;  printf("mlockall a echoue\\n");&lt;BR /&gt; }&lt;BR /&gt;&lt;BR /&gt; sched_setaffinity(0,1,&amp;amp;set);&lt;BR /&gt; priomax = sched_get_priority_max(SCHED_FIFO) ; /* Max priority */&lt;BR /&gt; param.sched_priority = priomax;&lt;BR /&gt; sched_setscheduler(0, SCHED_FIFO, &amp;amp;param);&lt;BR /&gt;&lt;BR /&gt; for (i=0;i&amp;lt;20;++i) {&lt;BR /&gt;  exemple_MOV_im();&lt;BR /&gt; }&lt;BR /&gt; return 0;&lt;BR /&gt;}&lt;BR /&gt;&lt;BR /&gt;This is executed on a Linux ia32 (fedora 11 with kernel 2.6.30.9-96.fc11.i686.PAE)&lt;BR /&gt;&lt;BR /&gt;When executing this I get :&lt;BR /&gt;&lt;BR /&gt;t2=2066&lt;BR /&gt;t2=2040&lt;BR /&gt;t2=1997&lt;BR /&gt;t2=1998&lt;BR /&gt;t2=1997&lt;BR /&gt;t2=1989&lt;BR /&gt;t2=1997&lt;BR /&gt;t2=1998&lt;BR /&gt;t2=1998&lt;BR /&gt;t2=1997&lt;BR /&gt;t2=1997&lt;BR /&gt;t2=1998&lt;BR /&gt;t2=1998&lt;BR /&gt;t2=1997&lt;BR /&gt;t2=1997&lt;BR /&gt;t2=1998&lt;BR /&gt;t2=1997&lt;BR /&gt;t2=1997&lt;BR /&gt;t2=1997&lt;BR /&gt;t2=1997&lt;BR /&gt;&lt;BR /&gt;Which is not fully repeatable but basically the pattern is the same:&lt;BR /&gt; &lt;BR /&gt;between 2 and 3 maximum time execution and then almost non varying execution.&lt;BR /&gt;Could you tell me what would explain the "2 and 3 maximum time execution" ?&lt;BR /&gt;&lt;BR /&gt;I would expect to have the first execution with maximum time (instruction &amp;amp; data cache load)&lt;BR /&gt;and then constant time execution. &lt;BR /&gt;&lt;BR /&gt;Note that the "mlockall, sched_setaffinity,sched_setscheduler" calls should ensure&lt;BR /&gt;maximum isolation because the system was booted with "isolcpus=1" which&lt;BR /&gt;ensure no other process can go to the CPU 1.&lt;BR /&gt;&lt;BR /&gt;CPU is Intel Core2 Quad CPU Q9550 @ 2.83GHz&lt;BR /&gt;same result (with different timing) on&lt;BR /&gt;Intel Xeon CPU X5472 @ 3.00GHz&lt;BR /&gt;&lt;BR /&gt;Any advice ? Explanation?&lt;BR /&gt;Our goal would be to have "predictable performance" fro some "basic" code.&lt;BR /&gt;Predictable meaning which can stay within a known performance interval.&lt;BR /&gt;</description>
      <pubDate>Thu, 15 Jul 2010 08:50:35 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/Variability-in-timing-measure-using-RDTSC/m-p/779211#M238</guid>
      <dc:creator>aeric</dc:creator>
      <dc:date>2010-07-15T08:50:35Z</dc:date>
    </item>
    <item>
      <title>Variability in timing measure using RDTSC</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/Variability-in-timing-measure-using-RDTSC/m-p/779212#M239</link>
      <description>Hi,&lt;BR /&gt;&lt;BR /&gt;It's a good question.&lt;BR /&gt;Firsrly, I like your code to set CPU mask and lock pages. But instead of&lt;BR /&gt; sched_setaffinity(0,1,&amp;amp;set);&lt;BR /&gt;there should be more correct to use&lt;BR /&gt; sched_setaffinity(0,&lt;B&gt;sizeof(set)&lt;/B&gt;,&amp;amp;set);&lt;BR /&gt;&lt;BR /&gt;As to instability on the first measurements, they are in my opinion, due to CPU instruction caches or pipe-line init.&lt;BR /&gt;But in general your code is run in OS environment and can be interupted by other devices/demons like timer, IO*, eth0* etc. Look at /proc/interrupts on Linux to see CPU-interupts.&lt;BR /&gt;So fluctuations in time-stamp-counters are possible on the same piece of code.&lt;BR /&gt;Therefore, I'd suggest using kind of statistical analisys of resuts to get predictable performance.&lt;BR /&gt;&lt;BR /&gt;For example, I got the following on my machine:&lt;BR /&gt;t2=4711&lt;BR /&gt;t2=4683&lt;BR /&gt;t2=4683&lt;BR /&gt;t2=4683&lt;BR /&gt;t2=4683&lt;BR /&gt;t2=4683&lt;BR /&gt;t2=4683&lt;BR /&gt;t2=4683&lt;BR /&gt;t2=18123&lt;BR /&gt;t2=4683&lt;BR /&gt;t2=4683&lt;BR /&gt;t2=4683&lt;BR /&gt;t2=4683&lt;BR /&gt;t2=4676&lt;BR /&gt;t2=4683&lt;BR /&gt;t2=4676&lt;BR /&gt;t2=4683&lt;BR /&gt;t2=4683&lt;BR /&gt;t2=4683&lt;BR /&gt;t2=4683&lt;BR /&gt;&lt;BR /&gt;</description>
      <pubDate>Tue, 27 Jul 2010 09:09:52 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/Variability-in-timing-measure-using-RDTSC/m-p/779212#M239</guid>
      <dc:creator>barragan_villanueva_</dc:creator>
      <dc:date>2010-07-27T09:09:52Z</dc:date>
    </item>
    <item>
      <title>Variability in timing measure using RDTSC</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/Variability-in-timing-measure-using-RDTSC/m-p/779213#M240</link>
      <description>Thank you for your answer,&lt;BR /&gt;&lt;BR /&gt;Sorry for the late answer but I didn't saw it before now.&lt;BR /&gt;(Is there a way to get mail notice of message follow-up?)&lt;BR /&gt;&lt;BR /&gt;Thanks you for noticing my typo about the sched_affinity call.&lt;BR /&gt;&lt;BR /&gt;Concerning the interrupt, I did do the test &lt;BR /&gt;on an isolated cpu (using isolcpus linux kernel option) &lt;BR /&gt;such that no can go to the isolated CPUs unless explicitely told by the user.&lt;BR /&gt;&lt;BR /&gt;I thought the interrupt mask followed the same scheme &lt;BR /&gt;(and I did deactivate irqbalance) but this does not seem to be the case.&lt;BR /&gt;I'll redo my test with irq affinity properly set.&lt;BR /&gt;&lt;BR /&gt;Concerning statistical analysis, I'm not interested in this approach because&lt;BR /&gt;I want to bound the worst case execution time.&lt;BR /&gt;&lt;BR /&gt;Filtering out first numbers may be ok as soon as later numbers are "stable enough".&lt;BR /&gt;</description>
      <pubDate>Tue, 04 Jan 2011 12:54:24 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/Variability-in-timing-measure-using-RDTSC/m-p/779213#M240</guid>
      <dc:creator>aeric</dc:creator>
      <dc:date>2011-01-04T12:54:24Z</dc:date>
    </item>
    <item>
      <title>Variability in timing measure using RDTSC</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/Variability-in-timing-measure-using-RDTSC/m-p/779214#M241</link>
      <description>&lt;DIV id="tiny_quote"&gt;&lt;DIV style="margin-left: 2px; margin-right: 2px;"&gt;Quoting &lt;A jquery1294409910507="63" rel="/en-us/services/profile/quick_profile.php?is_paid=&amp;amp;user_id=485484" href="https://community.intel.com/en-us/profile/485484/" class="basic"&gt;aeric&lt;/A&gt;&lt;/DIV&gt;&lt;DIV style="background-color: #e5e5e5; margin-left: 2px; margin-right: 2px; border: 1px inset; padding: 5px;"&gt;&lt;I&gt;Thank you for your answer,&lt;BR /&gt;&lt;BR /&gt;Sorry for the late answer but I didn't saw it before now.&lt;BR /&gt;(Is there a way to get mail notice of message follow-up?)&lt;BR /&gt;&lt;/I&gt;&lt;/DIV&gt;&lt;BR /&gt;There is a check box next to "Subscribed to this Thread" near the top of the page. If youclick onthis check box, you will get an email notification whenever someone is posting a new answer to this thread.&lt;/DIV&gt;</description>
      <pubDate>Fri, 07 Jan 2011 14:20:59 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/Variability-in-timing-measure-using-RDTSC/m-p/779214#M241</guid>
      <dc:creator>Thomas_W_Intel</dc:creator>
      <dc:date>2011-01-07T14:20:59Z</dc:date>
    </item>
    <item>
      <title>Variability in timing measure using RDTSC</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/Variability-in-timing-measure-using-RDTSC/m-p/779215#M242</link>
      <description>&lt;DIV id="tiny_quote"&gt;&lt;DIV style="margin-left: 2px; margin-right: 2px;"&gt;Quoting &lt;A jquery1294747351518="63" rel="/en-us/services/profile/quick_profile.php?is_paid=&amp;amp;user_id=485484" href="https://community.intel.com/en-us/profile/485484/" class="basic"&gt;aeric&lt;/A&gt;&lt;/DIV&gt;&lt;DIV style="background-color: #e5e5e5; margin-left: 2px; margin-right: 2px; border: 1px inset; padding: 5px;"&gt;&lt;I&gt;Concerning statistical analysis, I'm not interested in this approach because&lt;BR /&gt;I want to bound the worst case execution time.&lt;BR /&gt;&lt;BR /&gt;Filtering out first numbers may be ok as soon as later numbers are "stable enough".&lt;BR /&gt;&lt;/I&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;P&gt;&lt;BR /&gt;Speaking about &lt;EM&gt;&lt;STRONG&gt;statistical analysis &lt;/STRONG&gt;&lt;/EM&gt;I meant to do something like as follows: skip first numbers and calculate average of the others&lt;/P&gt;</description>
      <pubDate>Tue, 11 Jan 2011 12:49:44 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/Variability-in-timing-measure-using-RDTSC/m-p/779215#M242</guid>
      <dc:creator>barragan_villanueva_</dc:creator>
      <dc:date>2011-01-11T12:49:44Z</dc:date>
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