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    <title>topic Re: Larrabee will support SSE or not?  in Intel® ISA Extensions</title>
    <link>https://community.intel.com/t5/Intel-ISA-Extensions/Larrabee-will-support-SSE-or-not/m-p/881296#M2507</link>
    <description>&lt;DIV style="margin:0px;"&gt;
&lt;DIV id="quote_reply" style="width: 100%; margin-top: 5px;"&gt;
&lt;DIV style="margin-left:2px;margin-right:2px;"&gt;Quoting - &lt;A href="https://community.intel.com/en-us/profile/367365"&gt;tim18&lt;/A&gt;&lt;/DIV&gt;
&lt;DIV style="background-color:#E5E5E5; padding:5px;border: 1px; border-style: inset;margin-left:2px;margin-right:2px;"&gt;&lt;EM&gt;
&lt;DIV style="margin:0px;"&gt;&lt;/DIV&gt;
A different instruction set&lt;BR /&gt;&lt;/EM&gt;&lt;/DIV&gt;
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&lt;BR /&gt;What kind of answer is this?&lt;BR /&gt;&lt;BR /&gt;</description>
    <pubDate>Tue, 01 Sep 2009 22:20:17 GMT</pubDate>
    <dc:creator>levicki</dc:creator>
    <dc:date>2009-09-01T22:20:17Z</dc:date>
    <item>
      <title>Larrabee will support SSE or not?</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/Larrabee-will-support-SSE-or-not/m-p/881294#M2505</link>
      <description>&lt;P&gt;Larrabee will be compatible with SSE/SSE2/SSE3/SSE4 code or not?&lt;/P&gt;</description>
      <pubDate>Tue, 01 Sep 2009 17:50:52 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/Larrabee-will-support-SSE-or-not/m-p/881294#M2505</guid>
      <dc:creator>maa1</dc:creator>
      <dc:date>2009-09-01T17:50:52Z</dc:date>
    </item>
    <item>
      <title>Re: Larrabee will support SSE or not?</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/Larrabee-will-support-SSE-or-not/m-p/881295#M2506</link>
      <description>&lt;DIV style="margin:0px;"&gt;
&lt;DIV id="quote_reply" style="width: 100%; margin-top: 5px;"&gt;
&lt;DIV style="margin-left:2px;margin-right:2px;"&gt;Quoting - &lt;A href="https://community.intel.com/en-us/profile/441102"&gt;maa1&lt;/A&gt;&lt;/DIV&gt;
&lt;DIV style="background-color:#E5E5E5; padding:5px;border: 1px; border-style: inset;margin-left:2px;margin-right:2px;"&gt;&lt;EM&gt;
&lt;P&gt;Larrabee will be compatible with SSE/SSE2/SSE3/SSE4 code or not?&lt;/P&gt;
&lt;/EM&gt;&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;
A different instruction set&lt;BR /&gt;</description>
      <pubDate>Tue, 01 Sep 2009 20:59:26 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/Larrabee-will-support-SSE-or-not/m-p/881295#M2506</guid>
      <dc:creator>TimP</dc:creator>
      <dc:date>2009-09-01T20:59:26Z</dc:date>
    </item>
    <item>
      <title>Re: Larrabee will support SSE or not?</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/Larrabee-will-support-SSE-or-not/m-p/881296#M2507</link>
      <description>&lt;DIV style="margin:0px;"&gt;
&lt;DIV id="quote_reply" style="width: 100%; margin-top: 5px;"&gt;
&lt;DIV style="margin-left:2px;margin-right:2px;"&gt;Quoting - &lt;A href="https://community.intel.com/en-us/profile/367365"&gt;tim18&lt;/A&gt;&lt;/DIV&gt;
&lt;DIV style="background-color:#E5E5E5; padding:5px;border: 1px; border-style: inset;margin-left:2px;margin-right:2px;"&gt;&lt;EM&gt;
&lt;DIV style="margin:0px;"&gt;&lt;/DIV&gt;
A different instruction set&lt;BR /&gt;&lt;/EM&gt;&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;BR /&gt;What kind of answer is this?&lt;BR /&gt;&lt;BR /&gt;</description>
      <pubDate>Tue, 01 Sep 2009 22:20:17 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/Larrabee-will-support-SSE-or-not/m-p/881296#M2507</guid>
      <dc:creator>levicki</dc:creator>
      <dc:date>2009-09-01T22:20:17Z</dc:date>
    </item>
    <item>
      <title>Re: Larrabee will support SSE or not?</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/Larrabee-will-support-SSE-or-not/m-p/881297#M2508</link>
      <description>&lt;DIV style="margin:0px;"&gt;
&lt;DIV id="quote_reply" style="width: 100%; margin-top: 5px;"&gt;
&lt;DIV style="margin-left:2px;margin-right:2px;"&gt;Quoting - &lt;A href="https://community.intel.com/en-us/profile/61352"&gt;Igor Levicki&lt;/A&gt;&lt;/DIV&gt;
&lt;DIV style="background-color:#E5E5E5; padding:5px;border: 1px; border-style: inset;margin-left:2px;margin-right:2px;"&gt;&lt;EM&gt;
&lt;DIV style="margin:0px;"&gt;&lt;/DIV&gt;
&lt;BR /&gt;What kind of answer is this?&lt;BR /&gt;&lt;BR /&gt;&lt;/EM&gt;&lt;/DIV&gt;
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God and none other than Tim knows?&lt;BR /&gt;</description>
      <pubDate>Wed, 02 Sep 2009 03:49:12 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/Larrabee-will-support-SSE-or-not/m-p/881297#M2508</guid>
      <dc:creator>srimks</dc:creator>
      <dc:date>2009-09-02T03:49:12Z</dc:date>
    </item>
    <item>
      <title>Re: Larrabee will support SSE or not?</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/Larrabee-will-support-SSE-or-not/m-p/881298#M2509</link>
      <description>&lt;DIV style="margin:0px;"&gt;
&lt;DIV id="quote_reply" style="width: 100%; margin-top: 5px;"&gt;
&lt;DIV style="margin-left:2px;margin-right:2px;"&gt;Quoting - &lt;A href="https://community.intel.com/en-us/profile/441102"&gt;maa1&lt;/A&gt;&lt;/DIV&gt;
&lt;DIV style="background-color:#E5E5E5; padding:5px;border: 1px; border-style: inset;margin-left:2px;margin-right:2px;"&gt;&lt;EM&gt;
&lt;P&gt;Larrabee will be compatible with SSE/SSE2/SSE3/SSE4 code or not?&lt;/P&gt;
&lt;/EM&gt;&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;BR /&gt;See here for the SIMD instructions Larrabee will provide: &lt;A href="http://software.intel.com/en-us/articles/prototype-primitives-guide/"&gt;http://software.intel.com/en-us/articles/prototype-primitives-guide/&lt;/A&gt;&lt;BR /&gt;&lt;BR /&gt;You can guess how much sense it would make to support another (a lot less powerful) SIMD instruction set when there is no code that is binary compatible anyway.&lt;BR /&gt;&lt;BR /&gt;BTW, if you want to write code that can use the SSE instructions on CPUs as well as the LRBni on Larrabee you should take a look at &lt;A href="http://gitorious.org/vc"&gt;http://gitorious.org/vc&lt;/A&gt;&lt;BR /&gt;</description>
      <pubDate>Wed, 02 Sep 2009 08:11:42 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/Larrabee-will-support-SSE-or-not/m-p/881298#M2509</guid>
      <dc:creator>Matthias_Kretz</dc:creator>
      <dc:date>2009-09-02T08:11:42Z</dc:date>
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