<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Question about the PUSH instruction in Intel® ISA Extensions</title>
    <link>https://community.intel.com/t5/Intel-ISA-Extensions/Question-about-the-PUSH-instruction/m-p/894917#M2674</link>
    <description>&lt;P&gt;Looking through 3 versions of the references, I can't seem to find a clear description of the semantics that covers all forms of the instruction. Vol. 2B says that "the operand-size attribute of the current code segment determines the amount the stack pointer is decremented (2, 4, or 8 bytes)." Yet, the description of pushing immediate values states, "If the source operand is an immediate and its size is less than the address size of the stack, a sign-extended value is pushed on the stack."&lt;/P&gt;
&lt;P&gt;Does this imply that the address-size attributeof the stack segment cannot be larger than the operand-size attribute of the code segment? &lt;/P&gt;
&lt;P&gt;The computation of the operand sizes for segment registers other than FS and GS seems a bit ambiguous as well. I have heard that there are quite a few errors in the documentation of PUSH, but have never verified this, nor have I found the corrections anywhere.&lt;/P&gt;
&lt;P&gt;Working on a code analyzer, so I now need to hammer this out. Does anyone know of a complete, consistent, and correct description of PUSH?&lt;/P&gt;
&lt;P&gt;Thanks for any help.&lt;/P&gt;</description>
    <pubDate>Wed, 30 Apr 2008 22:55:24 GMT</pubDate>
    <dc:creator>millersd</dc:creator>
    <dc:date>2008-04-30T22:55:24Z</dc:date>
    <item>
      <title>Question about the PUSH instruction</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/Question-about-the-PUSH-instruction/m-p/894917#M2674</link>
      <description>&lt;P&gt;Looking through 3 versions of the references, I can't seem to find a clear description of the semantics that covers all forms of the instruction. Vol. 2B says that "the operand-size attribute of the current code segment determines the amount the stack pointer is decremented (2, 4, or 8 bytes)." Yet, the description of pushing immediate values states, "If the source operand is an immediate and its size is less than the address size of the stack, a sign-extended value is pushed on the stack."&lt;/P&gt;
&lt;P&gt;Does this imply that the address-size attributeof the stack segment cannot be larger than the operand-size attribute of the code segment? &lt;/P&gt;
&lt;P&gt;The computation of the operand sizes for segment registers other than FS and GS seems a bit ambiguous as well. I have heard that there are quite a few errors in the documentation of PUSH, but have never verified this, nor have I found the corrections anywhere.&lt;/P&gt;
&lt;P&gt;Working on a code analyzer, so I now need to hammer this out. Does anyone know of a complete, consistent, and correct description of PUSH?&lt;/P&gt;
&lt;P&gt;Thanks for any help.&lt;/P&gt;</description>
      <pubDate>Wed, 30 Apr 2008 22:55:24 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/Question-about-the-PUSH-instruction/m-p/894917#M2674</guid>
      <dc:creator>millersd</dc:creator>
      <dc:date>2008-04-30T22:55:24Z</dc:date>
    </item>
    <item>
      <title>Re: Question about the PUSH instruction</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/Question-about-the-PUSH-instruction/m-p/894918#M2675</link>
      <description>&lt;P&gt;Perhaps you were expecting the elements that influence the behavior differences between different flavors of PUSH should be intuitive and do not have branchy behavior. &lt;/P&gt;
&lt;P&gt;Basically, the operand size of a given instruction (on a per opcode basis, vs. per mnemonic) can be opcode-specific. However, the organization of the instruction reference pages are either per-mnemonic or grouping several mnemonic with the same general processing capabilities. It is quite often that the operand size of a given instruction is associated with the default osize attribute of the current code segment but there are several nuances that deviates from that generality and making things a bit complicated. &lt;/P&gt;
&lt;P&gt;If you look at the operation section, you'll see the somewhat complicated if/else structure illustrating the mode-specific behavior with a common pattern, the size granularity of data that are push/pop'ed either follow the default or at a different size via the use of Osize override prefix 66H. So in 64-bit segment, you have 8 byte (default) vs. 2 byte; in 32-bit segment you have 4 bytes (default) vs. 2 byte; in 16-bit segment, you have 2 byte (default) vs. 4 byte. &lt;/P&gt;
&lt;P&gt;The immediate flavor of PUSH adds a small twist (the operand size of the instruction can be different from the number bytes that are encoded as a immediate) to these behavior so that PUSH and POP can work together with either 64-bit, 32-bit, or 16-bit segments.Since the number of bytes being encoded in a PUSH instruction can be smaller than the data size that gets push on the stack, Sign-extension is applied to make up the difference is size.&lt;/P&gt;</description>
      <pubDate>Fri, 02 May 2008 23:04:42 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/Question-about-the-PUSH-instruction/m-p/894918#M2675</guid>
      <dc:creator>SHIH_K_Intel</dc:creator>
      <dc:date>2008-05-02T23:04:42Z</dc:date>
    </item>
    <item>
      <title>Re: Question about the PUSH instruction</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/Question-about-the-PUSH-instruction/m-p/894919#M2676</link>
      <description>Could you clarify the role of the address-size attribute of the stack segment in the operation of the push-immediate flavor?  
&lt;BR /&gt;
&lt;BR /&gt;The reference says that immediates are sign-extended if they are smaller than the stack-segment address-size attribute...does this imply that they are sign-extended to the stack-segment address size?
&lt;BR /&gt;
&lt;BR /&gt;The reference says that the stack pointer is decremented based on the operand size attribute of the code segment, so I hope that either the above is false, or there is a mechanism to prevent the stack-segment address size from being larger than the code segment operand size...
&lt;BR /&gt;
&lt;BR /&gt;Thanks in advance</description>
      <pubDate>Tue, 13 May 2008 14:56:34 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/Question-about-the-PUSH-instruction/m-p/894919#M2676</guid>
      <dc:creator>millersd</dc:creator>
      <dc:date>2008-05-13T14:56:34Z</dc:date>
    </item>
  </channel>
</rss>

