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    <title>topic SFENCE and peripheral devices in Intel® ISA Extensions</title>
    <link>https://community.intel.com/t5/Intel-ISA-Extensions/SFENCE-and-peripheral-devices/m-p/901985#M2781</link>
    <description>&lt;P&gt;&lt;FONT face="Verdana" size="2"&gt;Does SFENCE(MFENCE) instruction ensure that preceding memory writes are actually propagated to the system bus, so the writes are visible by bus master peripheral devices? Or does it work in conjunction with MESI protocol and is guaranteed to propagate writes only between CPUs/cores?&lt;/FONT&gt;&lt;/P&gt;</description>
    <pubDate>Mon, 15 Oct 2007 08:21:27 GMT</pubDate>
    <dc:creator>dm71</dc:creator>
    <dc:date>2007-10-15T08:21:27Z</dc:date>
    <item>
      <title>SFENCE and peripheral devices</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/SFENCE-and-peripheral-devices/m-p/901985#M2781</link>
      <description>&lt;P&gt;&lt;FONT face="Verdana" size="2"&gt;Does SFENCE(MFENCE) instruction ensure that preceding memory writes are actually propagated to the system bus, so the writes are visible by bus master peripheral devices? Or does it work in conjunction with MESI protocol and is guaranteed to propagate writes only between CPUs/cores?&lt;/FONT&gt;&lt;/P&gt;</description>
      <pubDate>Mon, 15 Oct 2007 08:21:27 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/SFENCE-and-peripheral-devices/m-p/901985#M2781</guid>
      <dc:creator>dm71</dc:creator>
      <dc:date>2007-10-15T08:21:27Z</dc:date>
    </item>
    <item>
      <title>Re: SFENCE and peripheral devices</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/SFENCE-and-peripheral-devices/m-p/901986#M2782</link>
      <description>&lt;P&gt;&lt;FONT face="Arial" size="2"&gt;We forwarded this question to our engineering contacts,one of whomresponded:&lt;/FONT&gt;&lt;/P&gt;
&lt;BLOCKQUOTE dir="ltr"&gt;
&lt;DIV align="left"&gt;&lt;SPAN class="671100214-16102007"&gt;&lt;FONT face="Arial" size="2"&gt;sfence does cause the so called "PCI posting" to be flushed to devices. &lt;/FONT&gt;&lt;/SPAN&gt;&lt;SPAN class="671100214-16102007"&gt;&lt;FONT face="Arial" size="2"&gt;The most common way to force a PCI posting flush is to do an mmio read from the device in question; per &lt;/FONT&gt;&lt;/SPAN&gt;&lt;SPAN class="671100214-16102007"&gt;&lt;FONT face="Arial" size="2"&gt;the PCI spec this will cause any buffered (posted) data to be flushed first.&lt;/FONT&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;/BLOCKQUOTE&gt;
&lt;DIV align="left"&gt;&lt;SPAN class="671100214-16102007"&gt;&lt;FONT face="Arial" size="2"&gt;==&lt;/FONT&gt;&lt;/SPAN&gt;&lt;/DIV&gt;
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      <pubDate>Tue, 16 Oct 2007 15:36:27 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/SFENCE-and-peripheral-devices/m-p/901986#M2782</guid>
      <dc:creator>Intel_Software_Netw1</dc:creator>
      <dc:date>2007-10-16T15:36:27Z</dc:date>
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