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    <title>topic Quote:Sergey Kostrov wrote: in Intel® ISA Extensions</title>
    <link>https://community.intel.com/t5/Intel-ISA-Extensions/How-to-assign-a-constant/m-p/928612#M3192</link>
    <description>&lt;P&gt;&lt;/P&gt;&lt;BLOCKQUOTE&gt;Sergey Kostrov wrote:&lt;BR /&gt;&lt;P&gt;&lt;/P&gt;
&lt;P&gt;&amp;gt;&amp;gt;...But XMM* is 128-bit (16 bytes) that a direct constant instruction can be in one chunk...&lt;/P&gt;
&lt;P&gt;What about throughput of instructions? For example, in case of a General Purpose &lt;STRONG&gt;MOV&lt;/STRONG&gt; instruction it is &lt;STRONG&gt;3&lt;/STRONG&gt; instructions in &lt;STRONG&gt;one&lt;/STRONG&gt; clock cycle. Take a look at Intel Optimization Reference for more information.&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;&lt;/P&gt;
&lt;P&gt;There is no&amp;nbsp;XMM* direct constant assign instruction yet. &amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Tue, 18 Jun 2013 21:58:19 GMT</pubDate>
    <dc:creator>CLi37</dc:creator>
    <dc:date>2013-06-18T21:58:19Z</dc:date>
    <item>
      <title>How to assign a constant?</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/How-to-assign-a-constant/m-p/928566#M3146</link>
      <description>&lt;P&gt;I do not think there are constant registers in x86. When I define a const array, x86 access these constants from a memory but not a direct constant in instruction. Any instructions can assign a 128bit/256bit constant to a SSE/AVX register?&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 30 Jan 2013 05:10:28 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/How-to-assign-a-constant/m-p/928566#M3146</guid>
      <dc:creator>CLi37</dc:creator>
      <dc:date>2013-01-30T05:10:28Z</dc:date>
    </item>
    <item>
      <title>Are you talking about C</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/How-to-assign-a-constant/m-p/928567#M3147</link>
      <description>&lt;P&gt;Are you talking about C programming?&amp;nbsp; About facilities of some specific compiler?&lt;/P&gt;
&lt;P&gt;How about a short example to make this specific?&lt;/P&gt;</description>
      <pubDate>Wed, 30 Jan 2013 13:13:57 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/How-to-assign-a-constant/m-p/928567#M3147</guid>
      <dc:creator>TimP</dc:creator>
      <dc:date>2013-01-30T13:13:57Z</dc:date>
    </item>
    <item>
      <title>Quote:chang-li wrote:</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/How-to-assign-a-constant/m-p/928568#M3148</link>
      <description>&lt;P&gt;&lt;/P&gt;&lt;BLOCKQUOTE&gt;chang-li wrote:&lt;BR /&gt;&lt;P&gt;&lt;/P&gt;
&lt;P&gt;I do not think there are constant registers in x86. When I define a const array, x86 access these constants from a memory but not a direct constant in instruction. Any instructions can assign a 128bit/256bit constant to a SSE/AVX register?&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;&lt;/P&gt;
&lt;P&gt;You can access XMMn registers with the help of inline assembly.This is my preffered method of SSE -aware programming.In order to load XMM register I use align 16 directive on my typedef structure which holds single precision fp and double precision fp scalar values arranged in 1D array&amp;nbsp;and I use movaps instruction to directly load XMMn registers.&lt;/P&gt;</description>
      <pubDate>Wed, 30 Jan 2013 13:57:44 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/How-to-assign-a-constant/m-p/928568#M3148</guid>
      <dc:creator>Bernard</dc:creator>
      <dc:date>2013-01-30T13:57:44Z</dc:date>
    </item>
    <item>
      <title>In C language</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/How-to-assign-a-constant/m-p/928569#M3149</link>
      <description>&lt;P&gt;In C language&lt;/P&gt;
&lt;P&gt;&lt;STRONG&gt;const unsigned char data[16] = {0xFF, 0x00, 0x01, 0xFF,0xFF, 0x00, 0x01, 0xFF,0xFF, 0x00, 0x01, 0xFF,0xFF, 0x00, 0x01, 0xFF};&lt;/STRONG&gt;&lt;BR /&gt;&lt;STRONG&gt;__m128i xmm0;&lt;/STRONG&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;STRONG&gt;xmm0 = _mm_loadu_si128((__m128i *)data);&amp;nbsp;&lt;/STRONG&gt;&lt;/P&gt;
&lt;P&gt;In ASM it becomes&lt;/P&gt;
&lt;P&gt;&lt;STRONG&gt;movdqa xmm0, PQDWORD PTR [esi+4]&lt;/STRONG&gt;&lt;/P&gt;
&lt;P&gt;What I expected is&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;STRONG&gt;movdqa xmm0, 0xFF0001FFFF0001FFFF0001FFFF0001FF&lt;/STRONG&gt;&lt;/P&gt;
&lt;P&gt;I could not find this form in assembly.&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;</description>
      <pubDate>Wed, 30 Jan 2013 14:25:00 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/How-to-assign-a-constant/m-p/928569#M3149</guid>
      <dc:creator>CLi37</dc:creator>
      <dc:date>2013-01-30T14:25:00Z</dc:date>
    </item>
    <item>
      <title>&gt;&gt;&gt;What I expected is</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/How-to-assign-a-constant/m-p/928570#M3150</link>
      <description>&lt;P&gt;&amp;gt;&amp;gt;&amp;gt;What I expected is&lt;/P&gt;
&lt;P&gt;&lt;STRONG&gt;movdqa xmm0, 0xFF0001FFFF0001FFFF0001FFFF0001FF&lt;/STRONG&gt;&lt;/P&gt;
&lt;P&gt;I could not find this form in assembly&amp;gt;&amp;gt;&amp;gt;&lt;/P&gt;
&lt;P&gt;In MASM I can load XMM register&amp;nbsp;directly by using declared primitive type with DUP directive.When using inline assembly you can load directly xmm register by using array name only and without using&amp;nbsp;pointer dereference operator.&lt;/P&gt;</description>
      <pubDate>Wed, 30 Jan 2013 15:50:45 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/How-to-assign-a-constant/m-p/928570#M3150</guid>
      <dc:creator>Bernard</dc:creator>
      <dc:date>2013-01-30T15:50:45Z</dc:date>
    </item>
    <item>
      <title>Do you have the right</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/How-to-assign-a-constant/m-p/928571#M3151</link>
      <description>&lt;P&gt;Do you have the right expression of inline assembly below?&amp;nbsp;&lt;BR /&gt;&lt;BR /&gt;&lt;STRONG&gt;movdqa xmm0, 0xFF0001FFFF0001FFFF0001FFFF0001FF&lt;/STRONG&gt;&lt;/P&gt;</description>
      <pubDate>Wed, 30 Jan 2013 22:34:00 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/How-to-assign-a-constant/m-p/928571#M3151</guid>
      <dc:creator>CLi37</dc:creator>
      <dc:date>2013-01-30T22:34:00Z</dc:date>
    </item>
    <item>
      <title>&gt;&gt;Do you have the right</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/How-to-assign-a-constant/m-p/928572#M3152</link>
      <description>&amp;gt;&amp;gt;Do you have the right expression of inline assembly below?
&amp;gt;&amp;gt;
&amp;gt;&amp;gt;movdqa xmm0, 0xFF0001FFFF0001FFFF0001FFFF0001FF

I checked the Instruction Set Reference ( Order Number: 325383-044US / August 2012 ) and I see that movdqa can not be used with constants. 

Please take a look at a page 572 of the manual. Here is a quote:
...
This instruction can be used to load an XMM register from a 128-bit memory location, to store the
contents of an XMM register into a 128-bit memory location, or to move data between two XMM registers.
...</description>
      <pubDate>Thu, 31 Jan 2013 01:44:00 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/How-to-assign-a-constant/m-p/928572#M3152</guid>
      <dc:creator>SergeyKostrov</dc:creator>
      <dc:date>2013-01-31T01:44:00Z</dc:date>
    </item>
    <item>
      <title>Iliya,</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/How-to-assign-a-constant/m-p/928573#M3153</link>
      <description>Iliya,

&amp;gt;&amp;gt;...In MASM I can &lt;STRONG&gt;load XMM register directly&lt;/STRONG&gt; by using declared primitive type &lt;STRONG&gt;with DUP&lt;/STRONG&gt;...

We really would like to see how you do it, please. Thanks in advance.</description>
      <pubDate>Thu, 31 Jan 2013 01:49:59 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/How-to-assign-a-constant/m-p/928573#M3153</guid>
      <dc:creator>SergeyKostrov</dc:creator>
      <dc:date>2013-01-31T01:49:59Z</dc:date>
    </item>
    <item>
      <title>Quote:Sergey Kostrov wrote:</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/How-to-assign-a-constant/m-p/928574#M3154</link>
      <description>&lt;P&gt;&lt;/P&gt;&lt;BLOCKQUOTE&gt;Sergey Kostrov wrote:&lt;BR /&gt;&lt;P&gt;&lt;/P&gt;
&lt;P&gt;Iliya,&lt;/P&gt;
&lt;P&gt;&amp;gt;&amp;gt;...In MASM I can &lt;STRONG&gt;load XMM register directly&lt;/STRONG&gt; by using declared primitive type &lt;STRONG&gt;with DUP&lt;/STRONG&gt;...&lt;/P&gt;
&lt;P&gt;We really would like to see how you do it, please. Thanks in advance.&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;&lt;/P&gt;
&lt;P&gt;Here is the code which calculates cosine function by Taylor&amp;nbsp; series expansion, please bear in mind that this code is not optimized and run slowly because of stack accesses which are not needed. I was able to load directly XMM register without dereferencing pointer.While reading the code please look at "coef" variables which are initialized to cosine series factorial denominators.&lt;/P&gt;
&lt;P&gt;.XMM&lt;BR /&gt;&amp;nbsp;.STACK 4096&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp;.DATA&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp; argument REAL4 0.0,0.0,0.0,0.0&lt;BR /&gt;&amp;nbsp;step REAL4 0.01,0.01,0.01,0.01&lt;BR /&gt;&amp;nbsp;hi_bound REAL4 1.0,1.0,1.0,1.0&lt;BR /&gt;&amp;nbsp;lo_bound REAL4 0.0,0.0,0.0,0.0&lt;BR /&gt;&amp;nbsp;up_range REAL4 1.0&lt;BR /&gt;&amp;nbsp;lo_range REAL4 0.0&lt;BR /&gt;&amp;nbsp;one REAL4 1.0,1.0,1.0,1.0&lt;BR /&gt;&amp;nbsp;counter BYTE 147&lt;BR /&gt;&amp;nbsp;coef1 REAL4 2.0,2.0,2.0,2.0 ;2!&lt;BR /&gt;&amp;nbsp;coef2 REAL4 24.0,24.0,24.0,24.0 ;4!&lt;BR /&gt;&amp;nbsp;coef3 REAL4 720.0,720.0,720.0,720.0 ;6!&lt;BR /&gt;&amp;nbsp;coef4 REAL4 40320.0,40320.0,40320.0,40320.0 ;8!&lt;BR /&gt;&amp;nbsp;coef5 REAL4 3628800.0,3628800.0,3628800.0,3628800.0 ;10!&lt;BR /&gt;&amp;nbsp;coef6 REAL4 479001600.0,479001600.0,479001600.0,479001600.0 ;12!&lt;BR /&gt;&amp;nbsp;coef7 REAL4 87178291200.0,87178291200.0,87178291200.0,87178291200.0 ;14!&lt;BR /&gt;&amp;nbsp;coef8 REAL4 20922789888000.0,20922789888000.0,20922789888000.0,20922789888000.0 ;16!&lt;BR /&gt;&amp;nbsp;coef9 REAL4 6402373705728000.0,6402373705728000.0,6402373705728000.0,6402373705728000.0 ;18!&lt;BR /&gt;&amp;nbsp;coef10 REAL4 2432902008176640000.0,2432902008176640000.0,2432902008176640000.0,2432902008176640000.0 ;20!&lt;BR /&gt;&amp;nbsp;coef11 REAL4 1124000727777607680000.0,1124000727777607680000.0,1124000727777607680000.0,1124000727777607680000.0 ;22!&lt;BR /&gt;&amp;nbsp;coef12 REAL4 620448401733239439360000.0,620448401733239439360000.0,620448401733239439360000.0,620448401733239439360000.0;24!&lt;BR /&gt;&amp;nbsp;coef13 REAL4 403291461126605635584000000.0,403291461126605635584000000.0,403291461126605635584000000.0,403291461126605635584000000.0 ;26!&lt;BR /&gt;&amp;nbsp;loop_counter BYTE 50&lt;BR /&gt;&amp;nbsp;loop_counter2 BYTE 25&lt;BR /&gt;&amp;nbsp;loop_compare REAL4 0.5,0.5,0.5,0.5&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp;.DATA?&lt;BR /&gt;&amp;nbsp;result REAL4 147 DUP(?)&lt;BR /&gt;&amp;nbsp;com_lo REAL4 4 DUP(?)&lt;BR /&gt;&amp;nbsp;com_hi REAL4 4 DUP(?)&lt;BR /&gt;&amp;nbsp;start_time DWORD ?&lt;BR /&gt;&amp;nbsp;end_time DWORD ?&lt;BR /&gt;&amp;nbsp;value REAL4 ?&lt;BR /&gt;&amp;nbsp;upper REAL4 1.0&lt;BR /&gt;&amp;nbsp;lower&amp;nbsp; REAL4 0.0&lt;BR /&gt;&amp;nbsp;counter_compare REAL4 4 DUP(?)&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp;.CODE&lt;BR /&gt;&amp;nbsp;main PROC&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp;push ebp&lt;BR /&gt;&amp;nbsp;mov esp,ebp&lt;BR /&gt;&amp;nbsp;sub esp,224&lt;BR /&gt;&amp;nbsp;mov cl,counter&lt;BR /&gt;&amp;nbsp;xor eax,eax&lt;BR /&gt;&amp;nbsp;xor ebx,ebx&lt;BR /&gt;&amp;nbsp;xorps xmm2,xmm2&lt;BR /&gt;&amp;nbsp;xorps xmm0,xmm0&lt;BR /&gt;&amp;nbsp;xorps xmm1,xmm1&lt;BR /&gt;&amp;nbsp;movups xmm5,argument&lt;BR /&gt;&amp;nbsp;movups xmm0,argument&lt;BR /&gt;&amp;nbsp;&lt;BR /&gt;&amp;nbsp;&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp;finit&lt;BR /&gt;&amp;nbsp;mWrite "Please enter a starting value for cosine calculation"&lt;BR /&gt;&amp;nbsp;call ReadFloat&lt;BR /&gt;&amp;nbsp;fst value&lt;BR /&gt;&amp;nbsp;call Crlf&lt;BR /&gt;&amp;nbsp;&lt;BR /&gt;&amp;nbsp;fld upper&lt;BR /&gt;&amp;nbsp;fcom value&lt;BR /&gt;&amp;nbsp;fnstsw ax&lt;BR /&gt;&amp;nbsp;sahf&lt;BR /&gt;&amp;nbsp;jnb error&lt;BR /&gt;&amp;nbsp;&lt;BR /&gt;&amp;nbsp;&lt;BR /&gt;&amp;nbsp;&lt;BR /&gt;&amp;nbsp;movss xmm5,value&lt;BR /&gt;&amp;nbsp;movss xmm5,value&lt;BR /&gt;&amp;nbsp;movss xmm5,value&lt;BR /&gt;&amp;nbsp;movss xmm5,value&lt;BR /&gt;L1:&lt;BR /&gt;&amp;nbsp;&amp;nbsp; movups xmm4,loop_compare&lt;BR /&gt;&amp;nbsp;&amp;nbsp; movups xmm3,xmm5&lt;BR /&gt;&amp;nbsp;&amp;nbsp; cmpps xmm3,xmm4,6&lt;BR /&gt;&amp;nbsp;&amp;nbsp; mov eax,OFFSET counter_compare&lt;BR /&gt;&amp;nbsp;&amp;nbsp; movups [eax],xmm3&lt;BR /&gt;&amp;nbsp;&amp;nbsp; mov ebx,[eax]&lt;BR /&gt;&amp;nbsp;&amp;nbsp; cmp ebx,0&lt;BR /&gt;&amp;nbsp;&amp;nbsp; jne L2&lt;BR /&gt;&amp;nbsp;&amp;nbsp; mov ebx,[eax+4]&lt;BR /&gt;&amp;nbsp;&amp;nbsp; cmp ebx,0&lt;BR /&gt;&amp;nbsp;&amp;nbsp; jne L2&lt;BR /&gt;&amp;nbsp;&amp;nbsp; mov ebx,[eax+8]&lt;BR /&gt;&amp;nbsp;&amp;nbsp; cmp ebx,0&lt;BR /&gt;&amp;nbsp;&amp;nbsp; jne L2&lt;BR /&gt;&amp;nbsp;&amp;nbsp; mov ebx,[eax+12]&lt;BR /&gt;&amp;nbsp;&amp;nbsp; cmp ebx,0&lt;BR /&gt;&amp;nbsp;&amp;nbsp; jne L2&lt;BR /&gt;&amp;nbsp;&amp;nbsp; movups xmm4,loop_compare&lt;BR /&gt;&amp;nbsp;&amp;nbsp; movups xmm3,xmm5&lt;BR /&gt;&amp;nbsp;&amp;nbsp; cmpps xmm3,xmm4,1&lt;BR /&gt;&amp;nbsp;&amp;nbsp; mov eax,OFFSET counter_compare&lt;BR /&gt;&amp;nbsp;&amp;nbsp; movups [eax],xmm3&lt;BR /&gt;&amp;nbsp;&amp;nbsp; mov ebx,[eax]&lt;BR /&gt;&amp;nbsp;&amp;nbsp; cmp ebx,11111111111111111111111111111111b&lt;BR /&gt;&amp;nbsp;&amp;nbsp; je L4&lt;BR /&gt;&amp;nbsp;&amp;nbsp; mov ebx,[eax+4]&lt;BR /&gt;&amp;nbsp;&amp;nbsp; cmp ebx,11111111111111111111111111111111b&lt;BR /&gt;&amp;nbsp;&amp;nbsp; je L4&lt;BR /&gt;&amp;nbsp;&amp;nbsp; mov ebx,[eax+8]&lt;BR /&gt;&amp;nbsp;&amp;nbsp; cmp ebx,11111111111111111111111111111111b&lt;BR /&gt;&amp;nbsp;&amp;nbsp; je L4&lt;BR /&gt;&amp;nbsp;&amp;nbsp; mov ebx,[eax+12]&lt;BR /&gt;&amp;nbsp;&amp;nbsp; cmp ebx,11111111111111111111111111111111b&lt;BR /&gt;&amp;nbsp;&amp;nbsp; je L4&lt;BR /&gt;&amp;nbsp;&amp;nbsp; xor eax,eax&lt;BR /&gt;&amp;nbsp;&amp;nbsp; jz L3&lt;BR /&gt;&amp;nbsp;L2:&lt;BR /&gt;&amp;nbsp;mov cl,loop_counter&lt;BR /&gt;&amp;nbsp;xor eax,eax&lt;BR /&gt;&amp;nbsp;jz L3&lt;BR /&gt;&amp;nbsp;L4:&lt;BR /&gt;&amp;nbsp;mov cl,loop_counter2&lt;BR /&gt;&amp;nbsp;xor eax,eax&lt;BR /&gt;&amp;nbsp;jz L3&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp;L3:&lt;BR /&gt;&amp;nbsp;mov edx,OFFSET step&lt;BR /&gt;&amp;nbsp;movups xmm4,[edx]&lt;BR /&gt;&amp;nbsp;addps xmm5,xmm4&lt;BR /&gt;&amp;nbsp; &lt;BR /&gt;&amp;nbsp;movups xmm7,xmm5&lt;BR /&gt;&amp;nbsp;movups xmm0,one&lt;BR /&gt;&amp;nbsp;mulps xmm7,xmm7 ;x^2&lt;BR /&gt;&amp;nbsp;movups xmm6,xmm7&lt;BR /&gt;&amp;nbsp;movups [ebp-16],xmm7 ;store x^7&lt;BR /&gt;&amp;nbsp;movups xmm2,coef1&lt;BR /&gt;&amp;nbsp;rcpps xmm1,xmm2 ;1/coef1&lt;BR /&gt;&amp;nbsp;mulps xmm1,xmm7&lt;BR /&gt;&amp;nbsp;subps xmm0,xmm1 ;1-x^2/2! xmm0 accumulator&lt;BR /&gt;&amp;nbsp;movups xmm7,[ebp-16]&lt;BR /&gt;&amp;nbsp;mulps xmm7,xmm6 ;x^4&lt;BR /&gt;&amp;nbsp;movups [ebp-32],xmm7 ;store x^4&lt;BR /&gt;&amp;nbsp;movups xmm2,coef2&lt;BR /&gt;&amp;nbsp;rcpps xmm1,xmm2 ;1/coef2&lt;BR /&gt;&amp;nbsp;mulps xmm1,xmm7&lt;BR /&gt;&amp;nbsp;addps xmm0,xmm1 ;1-1x^2/2!+x^4/4!&lt;BR /&gt;&amp;nbsp;movups xmm7,[ebp-32]&lt;BR /&gt;&amp;nbsp;mulps xmm7,xmm6 ;x^6&lt;BR /&gt;&amp;nbsp;movups [ebp-48],xmm7 ;store x^6&lt;BR /&gt;&amp;nbsp;movups xmm2,coef3&lt;BR /&gt;&amp;nbsp;rcpps xmm1,xmm2 ;1/coef3&lt;BR /&gt;&amp;nbsp;mulps xmm1,xmm7&lt;BR /&gt;&amp;nbsp;subps xmm0,xmm1 ;1-x^2/2!+x^4/4!-x^6/6!&lt;BR /&gt;&amp;nbsp;movups xmm7,[ebp-48]&lt;BR /&gt;&amp;nbsp;mulps xmm7,xmm6 ;x^8&lt;BR /&gt;&amp;nbsp;movups [ebp-64],xmm7 ;store x^8&lt;BR /&gt;&amp;nbsp;movups xmm2,coef4&lt;BR /&gt;&amp;nbsp;rcpps xmm1,xmm2 ;1/coef4&lt;BR /&gt;&amp;nbsp;mulps xmm1,xmm7&lt;BR /&gt;&amp;nbsp;addps xmm0,xmm1 ;1-x^2/2!+x^4/4!-x^6/6!+x^8/8!&lt;BR /&gt;&amp;nbsp;movups xmm7,[ebp-64]&lt;BR /&gt;&amp;nbsp;mulps xmm7,xmm6 ;x^10&lt;BR /&gt;&amp;nbsp;movups [ebp-80],xmm7 ;store x^10&lt;BR /&gt;&amp;nbsp;movups xmm2,coef5&lt;BR /&gt;&amp;nbsp;rcpps xmm1,xmm2 ;1/coef5&lt;BR /&gt;&amp;nbsp;mulps xmm1,xmm7&lt;BR /&gt;&amp;nbsp;subps xmm0,xmm1 ;1-x^2/2!+x^4/4!-x^6/6!+x^8/8!-x^10/10!&lt;BR /&gt;&amp;nbsp;movups xmm7,[ebp-80]&lt;BR /&gt;&amp;nbsp;mulps xmm7,xmm6 ;x^12&lt;BR /&gt;&amp;nbsp;movups [ebp-96],xmm7 ;store x^12&lt;BR /&gt;&amp;nbsp;movups xmm2,coef6&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;lt;---&amp;nbsp;&amp;nbsp;&amp;nbsp; XMM REGISTER IS DIRECTLY LOADED BY INITIALIZED COEF ARGUMENT&lt;BR /&gt;&amp;nbsp;rcpps xmm1,xmm2 ;1/coef6&lt;BR /&gt;&amp;nbsp;mulps xmm1,xmm7&lt;BR /&gt;&amp;nbsp;addps xmm0,xmm1 ;1-x^2/2!+x^4/4!-x^6/6!+x^8/8!-x^10/10!+x^12/12!&lt;BR /&gt;&amp;nbsp;movups xmm7,[ebp-96]&lt;BR /&gt;&amp;nbsp;mulps xmm7,xmm6;x^14&lt;BR /&gt;&amp;nbsp;movups [ebp-112],xmm7 ;store x^14&lt;BR /&gt;&amp;nbsp;movups xmm2,coef7&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;lt;---&amp;nbsp;&amp;nbsp;&amp;nbsp; XMM REGISTER IS DIRECTLY LOADED BY INITIALIZED COEF ARGUMENT&lt;BR /&gt;&amp;nbsp;rcpps xmm1,xmm2 ;1/coef7&lt;BR /&gt;&amp;nbsp;mulps xmm1,xmm7&lt;BR /&gt;&amp;nbsp;subps xmm0,xmm1 ;1-x^2/2!+x^4/4!-x^6/6!+x^8/8!-x^10/10!+x^12/12!-x^14/14!&lt;BR /&gt;&amp;nbsp;movups xmm7,[ebp-112]&lt;BR /&gt;&amp;nbsp;mulps xmm7,xmm6 ;x^16&lt;BR /&gt;&amp;nbsp;movups [ebp-128],xmm7 ;store x^16&lt;BR /&gt;&amp;nbsp;movups xmm2,coef8&lt;BR /&gt;&amp;nbsp;rcpps xmm1,xmm2 ;1/coef8&lt;BR /&gt;&amp;nbsp;mulps xmm1,xmm7&lt;BR /&gt;&amp;nbsp;addps xmm0,xmm1 ;1-x^2/2!+x^4/4!-x^6/6!+x^8/8!-x^10/10!+x^12/12!-x^14/14!+x^16/16!&lt;BR /&gt;&amp;nbsp;movups xmm7,[ebp-128]&lt;BR /&gt;&amp;nbsp;mulps xmm7,xmm6 ;x^18&lt;BR /&gt;&amp;nbsp;movups [ebp-144],xmm7;store x^18&lt;BR /&gt;&amp;nbsp;movups xmm2,coef9&lt;BR /&gt;&amp;nbsp;rcpps xmm1,xmm2 ;1/coef9&lt;BR /&gt;&amp;nbsp;mulps xmm1,xmm7&lt;BR /&gt;&amp;nbsp;subps xmm0,xmm1 ;1-x^2/2!+x^4/4!-x^6/6!+x^8/8!-x^10/10!+x^12/12!-x^14/14!+x^16/16!-x^18/18!&lt;BR /&gt;&amp;nbsp;movups xmm7,[ebp-144]&lt;BR /&gt;&amp;nbsp;mulps xmm7,xmm6 ;x^20&lt;BR /&gt;&amp;nbsp;movups [ebp-160],xmm7 ;store x^20&lt;BR /&gt;&amp;nbsp;movups xmm2,coef10&lt;BR /&gt;&amp;nbsp;rcpps xmm1,xmm2 ;1/coef10&lt;BR /&gt;&amp;nbsp;mulps xmm1,xmm7&lt;BR /&gt;&amp;nbsp;addps xmm0,xmm1 ;1-x^2/2!+x^4/4!-x^6/6!+x^8/8!-x^10/10!+x^12/12!-x^14/14!+x^16/16!-x^18/18!+x^20/20!&lt;BR /&gt;&amp;nbsp;movups xmm7,[ebp-160]&lt;BR /&gt;&amp;nbsp;mulps xmm7,xmm6 ;x^22&lt;BR /&gt;&amp;nbsp;movups [ebp-176],xmm7 ;store x^22&lt;BR /&gt;&amp;nbsp;movups xmm2,coef11&lt;BR /&gt;&amp;nbsp;rcpps xmm1,xmm2 ;1/coef11&lt;BR /&gt;&amp;nbsp;mulps xmm1,xmm7&lt;BR /&gt;&amp;nbsp;subps xmm0,xmm1;1-x^2/2!+x^4/4!-x^6/6!+x^8/8!-x^10/10!+x^12/12!-x^14/14!+x^16/16!-x^18/18!+x^20/20!-x^22/22! &lt;BR /&gt;&amp;nbsp;movups xmm7,[ebp-176]&lt;BR /&gt;&amp;nbsp;mulps xmm7,xmm6 ;x^24&lt;BR /&gt;&amp;nbsp;movups [ebp-192],xmm7 ;store x^24&lt;BR /&gt;&amp;nbsp;movups xmm2,coef12&lt;BR /&gt;&amp;nbsp;rcpps xmm1,xmm2 ;1/coef12&lt;BR /&gt;&amp;nbsp;mulps xmm1,xmm7&lt;BR /&gt;&amp;nbsp;addps xmm0,xmm1 ; +x^24/24!&lt;BR /&gt;&amp;nbsp;movups xmm7,[ebp-192]&lt;BR /&gt;&amp;nbsp;mulps xmm7,xmm6 ;x^26&lt;BR /&gt;&amp;nbsp;movups xmm2,coef13&lt;BR /&gt;&amp;nbsp;rcpps xmm1,xmm2 ;1/coef13&lt;BR /&gt;&amp;nbsp;mulps xmm1,xmm7&lt;BR /&gt;&amp;nbsp;subps xmm0,xmm1&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp;mov ebx,OFFSET result &lt;BR /&gt;&amp;nbsp;&lt;BR /&gt;&amp;nbsp;movups [ebx],xmm0&lt;BR /&gt;&amp;nbsp;fld&amp;nbsp; DWORD PTR[ebx]&lt;BR /&gt;&amp;nbsp;call WriteFloat&lt;BR /&gt;&amp;nbsp;call Crlf&lt;BR /&gt;&amp;nbsp;sub cl,1&lt;BR /&gt;&amp;nbsp;jnz L3&lt;BR /&gt;&amp;nbsp;xor eax,eax&lt;BR /&gt;&amp;nbsp;jz L5&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp;error:&lt;BR /&gt;&amp;nbsp;movups xmm5,argument&lt;BR /&gt;&amp;nbsp;xor eax,eax&lt;BR /&gt;&amp;nbsp;jz L3 &lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp;L5:&lt;BR /&gt;&amp;nbsp;exit&lt;BR /&gt;&amp;nbsp;main ENDP&lt;BR /&gt;&amp;nbsp;END main&lt;BR /&gt;&amp;nbsp;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;</description>
      <pubDate>Thu, 31 Jan 2013 06:31:57 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/How-to-assign-a-constant/m-p/928574#M3154</guid>
      <dc:creator>Bernard</dc:creator>
      <dc:date>2013-01-31T06:31:57Z</dc:date>
    </item>
    <item>
      <title>My code works with movups[d]</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/How-to-assign-a-constant/m-p/928575#M3155</link>
      <description>&lt;P&gt;My code works with movups&lt;D&gt; instruction,but testing movdqa has not been ever done.&lt;/D&gt;&lt;/P&gt;</description>
      <pubDate>Thu, 31 Jan 2013 13:45:34 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/How-to-assign-a-constant/m-p/928575#M3155</guid>
      <dc:creator>Bernard</dc:creator>
      <dc:date>2013-01-31T13:45:34Z</dc:date>
    </item>
    <item>
      <title>Thank you. I see that you're</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/How-to-assign-a-constant/m-p/928576#M3156</link>
      <description>Thank you. I see that you're using a different &lt;STRONG&gt;movups&lt;/STRONG&gt; instruction ( actually it is OK / page 623 in a manual ) and this is how the instruction is used in your codes.

&amp;gt;&amp;gt;...
&amp;gt;&amp;gt;&lt;STRONG&gt;one&lt;/STRONG&gt; &lt;STRONG&gt;REAL4&lt;/STRONG&gt; 1.0,1.0,1.0,1.0......Note: &lt;STRONG&gt;memory&lt;/STRONG&gt; is allocated here / It is &lt;STRONG&gt;Not&lt;/STRONG&gt; a literal constant
&amp;gt;&amp;gt;...
&amp;gt;&amp;gt;&lt;STRONG&gt;movups&lt;/STRONG&gt; xmm0, &lt;STRONG&gt;one&lt;/STRONG&gt;
&amp;gt;&amp;gt;...

It means, that a set of values &lt;STRONG&gt;1.0,1.0,1.0,1.0&lt;/STRONG&gt; is moved &lt;STRONG&gt;from a memory&lt;/STRONG&gt; (!) to &lt;STRONG&gt;xmm0&lt;/STRONG&gt; register. Once again, both instructions, that is &lt;STRONG&gt;movdqa&lt;/STRONG&gt; and &lt;STRONG&gt;movups&lt;/STRONG&gt;, can not work with constants by design.</description>
      <pubDate>Thu, 31 Jan 2013 13:46:48 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/How-to-assign-a-constant/m-p/928576#M3156</guid>
      <dc:creator>SergeyKostrov</dc:creator>
      <dc:date>2013-01-31T13:46:48Z</dc:date>
    </item>
    <item>
      <title>&gt;&gt;...both instructions, that</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/How-to-assign-a-constant/m-p/928577#M3157</link>
      <description>&amp;gt;&amp;gt;...both instructions, that is movdqa and movups, can not work with constants by design...

Here is a really small test case with inline assembler in a C/C++ test application:
...
_asm MOVDQA	xmm0, 0xFFFFFFFFFFFFFFFF
...
&lt;STRONG&gt;[ Compilation output ]&lt;/STRONG&gt;
...
..\prttests.cpp(8759) : error C2415: improper operand type
...</description>
      <pubDate>Thu, 31 Jan 2013 13:50:15 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/How-to-assign-a-constant/m-p/928577#M3157</guid>
      <dc:creator>SergeyKostrov</dc:creator>
      <dc:date>2013-01-31T13:50:15Z</dc:date>
    </item>
    <item>
      <title>Here is another small test</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/How-to-assign-a-constant/m-p/928578#M3158</link>
      <description>Here is another small test case:
...
		__m128 mmValue = { 1.0L, 2.0L, 3.0L, 4.0L };

	//	_asm MOVDQA	xmm0, 0xFFFFFFFFFFFFFFFF // error C2415: improper operand type
	//	_asm MOVUPS	xmm1, 0xFFFFFFFFFFFFFFFF // error C2415: improper operand type

		_asm MOVDQA	xmm0, [ mmValue ]
		_asm MOVUPS	xmm1, [ mmValue ]

		_asm MOVDQA	[ mmValue ], xmm2
		_asm MOVUPS	[ mmValue ], xmm3
...</description>
      <pubDate>Thu, 31 Jan 2013 13:57:19 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/How-to-assign-a-constant/m-p/928578#M3158</guid>
      <dc:creator>SergeyKostrov</dc:creator>
      <dc:date>2013-01-31T13:57:19Z</dc:date>
    </item>
    <item>
      <title>&gt;&gt;&gt;It means, that a set of</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/How-to-assign-a-constant/m-p/928579#M3159</link>
      <description>&lt;P&gt;&amp;gt;&amp;gt;&amp;gt;It means, that a set of values &lt;STRONG&gt;1.0,1.0,1.0,1.0&lt;/STRONG&gt; is moved &lt;STRONG&gt;from a memory&lt;/STRONG&gt; (!) to &lt;STRONG&gt;xmm0&lt;/STRONG&gt; register. Once again, both instructions, that is &lt;STRONG&gt;movdqa&lt;/STRONG&gt; and &lt;STRONG&gt;movups&lt;/STRONG&gt;, can not work with constants by design&amp;gt;&amp;gt;&amp;gt;&lt;/P&gt;
&lt;P&gt;I misunderstood the problem.In my code the load is coming from the memory and this was not the thread starter's question.The problem is "how to load XMM register with the immediate value".&lt;/P&gt;</description>
      <pubDate>Thu, 31 Jan 2013 14:04:04 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/How-to-assign-a-constant/m-p/928579#M3159</guid>
      <dc:creator>Bernard</dc:creator>
      <dc:date>2013-01-31T14:04:04Z</dc:date>
    </item>
    <item>
      <title>Exactly and I'd like to</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/How-to-assign-a-constant/m-p/928580#M3160</link>
      <description>Exactly and I'd like to change my former statement to:

&amp;gt;&amp;gt;...both instructions, that is &lt;STRONG&gt;movdqa&lt;/STRONG&gt; and &lt;STRONG&gt;movups&lt;/STRONG&gt;, can not work with &lt;STRONG&gt;literal constants&lt;/STRONG&gt; by design...</description>
      <pubDate>Thu, 31 Jan 2013 14:07:47 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/How-to-assign-a-constant/m-p/928580#M3160</guid>
      <dc:creator>SergeyKostrov</dc:creator>
      <dc:date>2013-01-31T14:07:47Z</dc:date>
    </item>
    <item>
      <title>&gt;&gt;&gt;// _asm MOVDQA xmm0,</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/How-to-assign-a-constant/m-p/928581#M3161</link>
      <description>&lt;P&gt;&amp;gt;&amp;gt;&amp;gt;// _asm MOVDQA xmm0, 0xFFFFFFFFFFFFFFFF // error C2415: improper operand type&amp;gt;&amp;gt;&amp;gt;&lt;/P&gt;
&lt;P&gt;Now I remember I have the same situation when I tried to load directly(immediate value)XMM registers.The second test is my preffered method of loading 1D vector represented by the 2 or 4 elements array into XMM register.You can also load the registers when passing structure members.For this use unaligned movups&lt;D&gt; instruction.&lt;/D&gt;&lt;/P&gt;</description>
      <pubDate>Thu, 31 Jan 2013 14:11:06 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/How-to-assign-a-constant/m-p/928581#M3161</guid>
      <dc:creator>Bernard</dc:creator>
      <dc:date>2013-01-31T14:11:06Z</dc:date>
    </item>
    <item>
      <title>Quote:Sergey Kostrov wrote:</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/How-to-assign-a-constant/m-p/928582#M3162</link>
      <description>&lt;P&gt;&lt;/P&gt;&lt;BLOCKQUOTE&gt;Sergey Kostrov wrote:&lt;BR /&gt;&lt;P&gt;&lt;/P&gt;
&lt;P&gt;Exactly and I'd like to change my former statement to:&lt;/P&gt;
&lt;P&gt;&amp;gt;&amp;gt;...both instructions, that is &lt;STRONG&gt;movdqa&lt;/STRONG&gt; and &lt;STRONG&gt;movups&lt;/STRONG&gt;, can not work with &lt;STRONG&gt;literal constants&lt;/STRONG&gt; by design...&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;&lt;/P&gt;
&lt;P&gt;Sadly Intel processor designers decided to not allow loading SSEn registers with the immediate values.I would like to know what is the cause of such a decision.&lt;/P&gt;</description>
      <pubDate>Thu, 31 Jan 2013 14:18:19 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/How-to-assign-a-constant/m-p/928582#M3162</guid>
      <dc:creator>Bernard</dc:creator>
      <dc:date>2013-01-31T14:18:19Z</dc:date>
    </item>
    <item>
      <title>&gt;&gt;one REAL4 1.0,1.0,1.0,1.0..</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/How-to-assign-a-constant/m-p/928583#M3163</link>
      <description>&lt;P&gt;&amp;gt;&amp;gt;&lt;STRONG&gt;one&lt;/STRONG&gt;&amp;nbsp;&lt;STRONG&gt;REAL4&lt;/STRONG&gt;&amp;nbsp;1.0,1.0,1.0,1.0......Note:&amp;nbsp;&lt;STRONG&gt;memory&lt;/STRONG&gt;&amp;nbsp;is allocated here / It is&amp;nbsp;&lt;STRONG&gt;Not&lt;/STRONG&gt;&amp;nbsp;a literal constant&lt;BR /&gt;&amp;gt;&amp;gt;&lt;STRONG&gt;movups&lt;/STRONG&gt;&amp;nbsp;xmm0,&amp;nbsp;&lt;STRONG&gt;one&lt;/STRONG&gt;&lt;/P&gt;
&lt;P&gt;It also assing xmm0 to a value of a vector with 4 components.&lt;/P&gt;
&lt;P&gt;&lt;STRONG&gt;"how to load XMM register with the immediate value"&lt;/STRONG&gt;&lt;/P&gt;
&lt;P&gt;yes, this is the exact question. Looks answer is no. So following code&lt;/P&gt;
&lt;P&gt;&lt;STRONG&gt;movups xmm0,one&lt;/STRONG&gt;&lt;/P&gt;
&lt;P&gt;because the data one was loaded from memory, the algorithm is not all register based, in which the cache access may be related. The performance will be unexpected. The optimization on SSE/AVX may be collapsed.&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;</description>
      <pubDate>Thu, 31 Jan 2013 14:36:49 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/How-to-assign-a-constant/m-p/928583#M3163</guid>
      <dc:creator>CLi37</dc:creator>
      <dc:date>2013-01-31T14:36:49Z</dc:date>
    </item>
    <item>
      <title>&gt;&gt;...The performance will be</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/How-to-assign-a-constant/m-p/928584#M3164</link>
      <description>&amp;gt;&amp;gt;...The performance will be unexpected. The optimization on SSE/AVX may be collapsed...

These are a different set of issues ( actually I don't see any problems here / this is how Intel designed these instructions ). The instruction formats are in the manual and please take a look. Here is another test case ( compiled with Intel C++ compiler ):
...
	__m128 mmValue0 = { 1.0L, 2.0L, 3.0L, 4.0L };
	__m128 mmValue1 = { 5.0L, 6.0L, 7.0L, 8.0L };

	_asm MOVDQA	xmm0, 0xFFFFFFFFFFFFFFFF	// Microsoft C++ compiler: Error C2415: improper operand type
	_asm MOVUPS	xmm1, 0xFFFFFFFFFFFFFFFF	// Microsoft C++ compiler: Error C2415: improper operand type

	_asm MOVDQA	xmm0, xmmword ptr [ mmValue0 ]
	_asm MOVUPS	xmm1, xmmword ptr [ mmValue1 ]

	_asm MOVDQA	xmmword ptr [ mmValue0 ], xmm1
	_asm MOVUPS	xmmword ptr [ mmValue1 ], xmm0
...

&lt;STRONG&gt;[ Intel C++ compiler output ]&lt;/STRONG&gt;
...
..\PrtTests.cpp(8762): (col. 8) error: &lt;STRONG&gt;Unsupported instruction form&lt;/STRONG&gt; in asm instruction movdqa.
..\PrtTests.cpp(8763): (col. 8) error: &lt;STRONG&gt;Unsupported instruction form&lt;/STRONG&gt; in asm instruction movups.
(0): catastrophic error: fatal error: compilation terminated
...</description>
      <pubDate>Thu, 31 Jan 2013 14:52:41 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/How-to-assign-a-constant/m-p/928584#M3164</guid>
      <dc:creator>SergeyKostrov</dc:creator>
      <dc:date>2013-01-31T14:52:41Z</dc:date>
    </item>
    <item>
      <title>Because of the design of</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/How-to-assign-a-constant/m-p/928585#M3165</link>
      <description>&lt;P&gt;Because of the design of those SSEn&amp;nbsp; load/store instructions there will be some performance penalty when the data needs to be loaded first time from the memory.&lt;/P&gt;
&lt;P&gt;Loading of the XMM register with the pre-initialized structure member.&lt;/P&gt;
&lt;P&gt;SinVector sinvec1 = {-0.1666666,-0.1666666,-0.1666666,-0.1666666},*sinvec1ptr; sinvec1ptr = &amp;amp;sinvec1 // structure initialization&lt;/P&gt;
&lt;P&gt;Loading of the member&lt;/P&gt;
&lt;P&gt;movups xmm1,sinvec1&lt;/P&gt;
&lt;P&gt;By using custom typedef structure of array data type which is aligned on 16 bytes boundaries I can use movaps&lt;D&gt; instructions.&lt;/D&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 31 Jan 2013 15:06:00 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/How-to-assign-a-constant/m-p/928585#M3165</guid>
      <dc:creator>Bernard</dc:creator>
      <dc:date>2013-01-31T15:06:00Z</dc:date>
    </item>
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