<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Intel MIC(Many Integrated Core) in Intel® ISA Extensions</title>
    <link>https://community.intel.com/t5/Intel-ISA-Extensions/Intel-MIC-Many-Integrated-Core/m-p/790648#M404</link>
    <description>&lt;DIV id="tiny_quote"&gt;
                &lt;DIV style="margin-left: 2px; margin-right: 2px;"&gt;Quoting &lt;A rel="/en-us/services/profile/quick_profile.php?is_paid=&amp;amp;user_id=520976" class="basic" href="https://community.intel.com/en-us/profile/520976/"&gt;zhangxiuxia&lt;/A&gt;&lt;/DIV&gt;
                &lt;DIV style="background-color: #e5e5e5; padding: 5px; border: 1px; border-style: inset; margin-left: 2px; margin-right: 2px;"&gt;&lt;I&gt;icc -V&lt;BR /&gt;&lt;BR /&gt;Intel C Intel 64 Compiler XE including Intel MIC Architecture for Linux, Version Mainline.036 Alpha Build 20110201&lt;BR /&gt;&lt;BR /&gt;&lt;/I&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;P&gt;&lt;/P&gt;No, not public, it was distributed under a non-disclosure agreement. &lt;BR /&gt;</description>
    <pubDate>Wed, 20 Jul 2011 12:03:29 GMT</pubDate>
    <dc:creator>TimP</dc:creator>
    <dc:date>2011-07-20T12:03:29Z</dc:date>
    <item>
      <title>Intel MIC(Many Integrated Core)</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/Intel-MIC-Many-Integrated-Core/m-p/790638#M394</link>
      <description>AVX now is a thing of past. &lt;BR /&gt;Intel has producted a new kind of processor architecture&lt;BR /&gt;MIC. It 's works like GPU,many threads, but much easier to programming than GPU.&lt;BR /&gt;&lt;BR /&gt;I have a question about MIC .&lt;BR /&gt;&lt;BR /&gt;I write a program using MIC intrinsics , it works ok.&lt;BR /&gt;&lt;BR /&gt;when I using icc -S to generator ,it works Ok too.&lt;BR /&gt;&lt;BR /&gt;but when I using&lt;BR /&gt;icc -offload-build -c testMIC.s &lt;BR /&gt;icc -c testMIC.s &lt;BR /&gt;&lt;BR /&gt;it report many errors. &lt;BR /&gt;diag_spmvMIC.s:43: Error: no such instruction: `vkmov %eax,%k1'&lt;BR /&gt;diag_spmvMIC.s:146: Error: no such instruction: `vloadunpackhd 64(%r13,%r14,4){nt},%v0'&lt;BR /&gt;diag_spmvMIC.s:148: Error: no such instruction: `vloadunpackld (%r13,%r14,4){nt},%v0'&lt;BR /&gt;diag_spmvMIC.s:162: Error: no such instruction: `vloadq 176(%rsp){1to8},%v3'&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;Do any one using MIC give me some hint?&lt;BR /&gt;</description>
      <pubDate>Tue, 12 Jul 2011 12:19:49 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/Intel-MIC-Many-Integrated-Core/m-p/790638#M394</guid>
      <dc:creator>zhangxiuxia</dc:creator>
      <dc:date>2011-07-12T12:19:49Z</dc:date>
    </item>
    <item>
      <title>Intel MIC(Many Integrated Core)</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/Intel-MIC-Many-Integrated-Core/m-p/790639#M395</link>
      <description>&lt;DIV id="tiny_quote"&gt;
                &lt;DIV style="margin-left: 2px; margin-right: 2px;"&gt;Quoting &lt;A rel="/en-us/services/profile/quick_profile.php?is_paid=&amp;amp;user_id=520976" class="basic" href="https://community.intel.com/en-us/profile/520976/"&gt;zhangxiuxia&lt;/A&gt;&lt;/DIV&gt;
                &lt;DIV style="background-color: #e5e5e5; padding: 5px; border: 1px; border-style: inset; margin-left: 2px; margin-right: 2px;"&gt;&lt;I&gt;AVX now is a thing of past.&lt;BR /&gt;&lt;/I&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I beg to differ. AVX2 largely overlaps with LRBni, and can be extended up to 1024-bit operations. The latter property can be used to execute them in four cycles on 256-bit units, offering great opportunity for clock gating and thus massively reducing the power consumption of the out-of-order execution logic.&lt;/P&gt;&lt;P&gt;In other words, future high-end desktop CPUs could closely compete with the MICs in terms of throughput and power consumption.&lt;/P&gt;&lt;P&gt;CPUs have unique advantages though: out-of-order execution allows to keep a low number of threads, which means each of them get a large share of cache space. This improves the hit rates, which in turn lowers bandwidth needs and power consumption higher up. Lots of workloads also have large portions of serial code, for which the high frequency and low latency of the CPU is superior. So even with a lower peak peformance, the CPU can outperform other architectures in practice.&lt;/P&gt;&lt;P&gt;The MICs will fend off GPUs in the HPC market for a while, but in the longer term a CPU with AVX-1024 will be an all-round better option.&lt;/P&gt;</description>
      <pubDate>Tue, 12 Jul 2011 15:04:36 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/Intel-MIC-Many-Integrated-Core/m-p/790639#M395</guid>
      <dc:creator>capens__nicolas</dc:creator>
      <dc:date>2011-07-12T15:04:36Z</dc:date>
    </item>
    <item>
      <title>Intel MIC(Many Integrated Core)</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/Intel-MIC-Many-Integrated-Core/m-p/790640#M396</link>
      <description>&lt;P&gt;Your assembler does not recognize LRBni.&lt;/P&gt;</description>
      <pubDate>Wed, 13 Jul 2011 01:49:43 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/Intel-MIC-Many-Integrated-Core/m-p/790640#M396</guid>
      <dc:creator>styc</dc:creator>
      <dc:date>2011-07-13T01:49:43Z</dc:date>
    </item>
    <item>
      <title>Intel MIC(Many Integrated Core)</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/Intel-MIC-Many-Integrated-Core/m-p/790641#M397</link>
      <description>Which assembler should I use.?&lt;BR /&gt;&lt;BR /&gt;if ICC can compile larabee intrinsics , it should support LRBni,because intrinsics is just a &lt;BR /&gt;&lt;H2&gt;encapsulation of assembly instructions. &lt;/H2&gt;&lt;BR /&gt;</description>
      <pubDate>Wed, 13 Jul 2011 02:56:56 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/Intel-MIC-Many-Integrated-Core/m-p/790641#M397</guid>
      <dc:creator>zhangxiuxia</dc:creator>
      <dc:date>2011-07-13T02:56:56Z</dc:date>
    </item>
    <item>
      <title>Intel MIC(Many Integrated Core)</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/Intel-MIC-Many-Integrated-Core/m-p/790642#M398</link>
      <description>I suppose that if you have icc emit binary directly, there should be no problem; but if you have icc produce assembly source then assemble it, icc would most likely just delegate the assembling work to the system assembler, which unfortunately does not speak LRBni.</description>
      <pubDate>Wed, 13 Jul 2011 07:00:45 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/Intel-MIC-Many-Integrated-Core/m-p/790642#M398</guid>
      <dc:creator>styc</dc:creator>
      <dc:date>2011-07-13T07:00:45Z</dc:date>
    </item>
    <item>
      <title>Intel MIC(Many Integrated Core)</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/Intel-MIC-Many-Integrated-Core/m-p/790643#M399</link>
      <description>It's right , when I compile c files to binary object file ,it's ok.&lt;BR /&gt;But I use icc to produce assembly and then compile ,the compiler gives me error hints.&lt;BR /&gt;&lt;BR /&gt;"GNU as " and "GNU C" cannot work with such porgram.&lt;BR /&gt;ICCdoesnot work ,too.&lt;BR /&gt;How can I do , if I want to compile assembly programthat has LRBni in it.&lt;BR /&gt;&lt;BR /&gt;</description>
      <pubDate>Thu, 14 Jul 2011 03:24:26 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/Intel-MIC-Many-Integrated-Core/m-p/790643#M399</guid>
      <dc:creator>zhangxiuxia</dc:creator>
      <dc:date>2011-07-14T03:24:26Z</dc:date>
    </item>
    <item>
      <title>Intel MIC(Many Integrated Core)</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/Intel-MIC-Many-Integrated-Core/m-p/790644#M400</link>
      <description>Execuse me for my ignorance of AVX2 and my incorrect words. &lt;BR /&gt;I just learned LRB about its features of "many core, many threads,512 bit vector operation "&lt;BR /&gt;Have little knowledge about avx2 . &lt;BR /&gt;LRB has its own limits , 2 pipeline and in order execute and lower frequency.(alghou better than gpu )&lt;BR /&gt;Avx2 sounds more promising.&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;</description>
      <pubDate>Thu, 14 Jul 2011 13:06:20 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/Intel-MIC-Many-Integrated-Core/m-p/790644#M400</guid>
      <dc:creator>zhangxiuxia</dc:creator>
      <dc:date>2011-07-14T13:06:20Z</dc:date>
    </item>
    <item>
      <title>Intel MIC(Many Integrated Core)</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/Intel-MIC-Many-Integrated-Core/m-p/790645#M401</link>
      <description>What Intel compiler version are you using?&lt;DIV&gt;Is publicily avaiable?&lt;/DIV&gt;</description>
      <pubDate>Tue, 19 Jul 2011 12:49:15 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/Intel-MIC-Many-Integrated-Core/m-p/790645#M401</guid>
      <dc:creator>rtfss1gmail_com</dc:creator>
      <dc:date>2011-07-19T12:49:15Z</dc:date>
    </item>
    <item>
      <title>Intel MIC(Many Integrated Core)</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/Intel-MIC-Many-Integrated-Core/m-p/790646#M402</link>
      <description>icc --version&lt;BR /&gt;&lt;BR /&gt;icc (ICC) Mainline 20110201&lt;BR /&gt;Copyright (C) 1985-2010 Intel Corporation. All rights reserved.</description>
      <pubDate>Wed, 20 Jul 2011 07:03:29 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/Intel-MIC-Many-Integrated-Core/m-p/790646#M402</guid>
      <dc:creator>zhangxiuxia</dc:creator>
      <dc:date>2011-07-20T07:03:29Z</dc:date>
    </item>
    <item>
      <title>Intel MIC(Many Integrated Core)</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/Intel-MIC-Many-Integrated-Core/m-p/790647#M403</link>
      <description>icc -V&lt;BR /&gt;&lt;BR /&gt;Intel C Intel 64 Compiler XE including Intel MIC Architecture for Linux, Version Mainline.036 Alpha Build 20110201&lt;BR /&gt;Copyright (C) 1985-2010 Intel Corporation. All rights reserved.&lt;BR /&gt;&lt;BR /&gt;icc: NOTE: The Beta evaluation period for this product ends on 31-dec-2012 UTC.&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;I donot know whether it is publicily available . &lt;BR /&gt;our lab bought the machine and install the compiler.</description>
      <pubDate>Wed, 20 Jul 2011 07:10:17 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/Intel-MIC-Many-Integrated-Core/m-p/790647#M403</guid>
      <dc:creator>zhangxiuxia</dc:creator>
      <dc:date>2011-07-20T07:10:17Z</dc:date>
    </item>
    <item>
      <title>Intel MIC(Many Integrated Core)</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/Intel-MIC-Many-Integrated-Core/m-p/790648#M404</link>
      <description>&lt;DIV id="tiny_quote"&gt;
                &lt;DIV style="margin-left: 2px; margin-right: 2px;"&gt;Quoting &lt;A rel="/en-us/services/profile/quick_profile.php?is_paid=&amp;amp;user_id=520976" class="basic" href="https://community.intel.com/en-us/profile/520976/"&gt;zhangxiuxia&lt;/A&gt;&lt;/DIV&gt;
                &lt;DIV style="background-color: #e5e5e5; padding: 5px; border: 1px; border-style: inset; margin-left: 2px; margin-right: 2px;"&gt;&lt;I&gt;icc -V&lt;BR /&gt;&lt;BR /&gt;Intel C Intel 64 Compiler XE including Intel MIC Architecture for Linux, Version Mainline.036 Alpha Build 20110201&lt;BR /&gt;&lt;BR /&gt;&lt;/I&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;P&gt;&lt;/P&gt;No, not public, it was distributed under a non-disclosure agreement. &lt;BR /&gt;</description>
      <pubDate>Wed, 20 Jul 2011 12:03:29 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/Intel-MIC-Many-Integrated-Core/m-p/790648#M404</guid>
      <dc:creator>TimP</dc:creator>
      <dc:date>2011-07-20T12:03:29Z</dc:date>
    </item>
  </channel>
</rss>

