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    <title>topic Could you find a more up to in Intel® ISA Extensions</title>
    <link>https://community.intel.com/t5/Intel-ISA-Extensions/Unable-to-ative-the-SSE-nstruction-set-byadding-compile-flag/m-p/987283#M4764</link>
    <description>&lt;P&gt;Could you find a more up to date build of gcc for your OS?&amp;nbsp; The response posted looks like your CPU has been taken for an AMD.&lt;/P&gt;
&lt;P&gt;core2, unfortunately, is ambiguous, as early core2 (including my last one) didn't support SSE4.1, while recent versions do, so it won't be surprising if gcc doesn't do a lot for you with that option.&lt;/P&gt;
&lt;P&gt;On the old core2, with the gcc versions available back then, I used stuff like -march=pentium4 (if 32-bit).&amp;nbsp; -mssse3 wasn't as important for gcc as for icc (of course you want that or -msse3 to support complex arithmetic).&amp;nbsp; For the older gcc on the newer core2 with sse4.1, you may want&lt;/P&gt;
&lt;P&gt;-mtune=barcelona to encourage the compiler to use some 128-bit moves.&amp;nbsp; gcc was correct in preferring to split many 128-bit moves on the older core2.&lt;/P&gt;</description>
    <pubDate>Thu, 05 Sep 2013 15:00:36 GMT</pubDate>
    <dc:creator>TimP</dc:creator>
    <dc:date>2013-09-05T15:00:36Z</dc:date>
    <item>
      <title>Unable to ative the SSE nstruction set byadding compile flag “march=native” in gcc</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/Unable-to-ative-the-SSE-nstruction-set-byadding-compile-flag/m-p/987281#M4762</link>
      <description>&lt;P&gt;My machine is Core2 microarchitecture and I try to compile some arithmetic codes by using the SSE instruction set. I search on the web and official manual, the answer is everything I need to do （in simplest way）&amp;nbsp; to add the flag: march=native, because my chip support SSE. But when I use "gcc -march=native -Q --help=target -v" to check if the flag really works, the results display on the screen is a little bit beyond expectation, like：&lt;/P&gt;
&lt;P&gt;-msse [disabled]&lt;/P&gt;
&lt;P&gt;-msse2 [disabled]&lt;/P&gt;
&lt;P&gt;-msse2avx [disabled]&lt;/P&gt;
&lt;P&gt;-msse3 [disabled]&lt;/P&gt;
&lt;P&gt;-msse4 [disabled]&lt;/P&gt;
&lt;P&gt;-msse4.1 [disabled]&lt;/P&gt;
&lt;P&gt;-msse4.2 [disabled]&lt;/P&gt;
&lt;P&gt;-msse4a [disabled]&lt;/P&gt;
&lt;P&gt;-msse5&lt;/P&gt;
&lt;P&gt;-msseregparm [disabled]&lt;/P&gt;
&lt;P&gt;-mssse3 [disabled]&lt;/P&gt;
&lt;P&gt;I find all the SSE (even MMX) is disabled. Can any body tell me why and how to solve it? Many thanks！&lt;/P&gt;
&lt;P&gt;&lt;BR /&gt; PS: I know,an alternative way to active the option is to add the flags like -mmsse ...manually. But, I am just curiosity, why march=native doesn't works in my system:core2,Ubuntu 12.04(64bit system), gcc 4.6.3&lt;/P&gt;</description>
      <pubDate>Sat, 31 Aug 2013 10:25:38 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/Unable-to-ative-the-SSE-nstruction-set-byadding-compile-flag/m-p/987281#M4762</guid>
      <dc:creator>Chenjie_Y_</dc:creator>
      <dc:date>2013-08-31T10:25:38Z</dc:date>
    </item>
    <item>
      <title>I didn't try to use -march</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/Unable-to-ative-the-SSE-nstruction-set-byadding-compile-flag/m-p/987282#M4763</link>
      <description>I didn't try to use -march=native option but I know that the switch -m[ instruction set code ] ( like, -msse ) should work. If it doesn't work when using gcc 4.6.3 than this is a possible bug in the compiler.</description>
      <pubDate>Thu, 05 Sep 2013 13:39:18 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/Unable-to-ative-the-SSE-nstruction-set-byadding-compile-flag/m-p/987282#M4763</guid>
      <dc:creator>SergeyKostrov</dc:creator>
      <dc:date>2013-09-05T13:39:18Z</dc:date>
    </item>
    <item>
      <title>Could you find a more up to</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/Unable-to-ative-the-SSE-nstruction-set-byadding-compile-flag/m-p/987283#M4764</link>
      <description>&lt;P&gt;Could you find a more up to date build of gcc for your OS?&amp;nbsp; The response posted looks like your CPU has been taken for an AMD.&lt;/P&gt;
&lt;P&gt;core2, unfortunately, is ambiguous, as early core2 (including my last one) didn't support SSE4.1, while recent versions do, so it won't be surprising if gcc doesn't do a lot for you with that option.&lt;/P&gt;
&lt;P&gt;On the old core2, with the gcc versions available back then, I used stuff like -march=pentium4 (if 32-bit).&amp;nbsp; -mssse3 wasn't as important for gcc as for icc (of course you want that or -msse3 to support complex arithmetic).&amp;nbsp; For the older gcc on the newer core2 with sse4.1, you may want&lt;/P&gt;
&lt;P&gt;-mtune=barcelona to encourage the compiler to use some 128-bit moves.&amp;nbsp; gcc was correct in preferring to split many 128-bit moves on the older core2.&lt;/P&gt;</description>
      <pubDate>Thu, 05 Sep 2013 15:00:36 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/Unable-to-ative-the-SSE-nstruction-set-byadding-compile-flag/m-p/987283#M4764</guid>
      <dc:creator>TimP</dc:creator>
      <dc:date>2013-09-05T15:00:36Z</dc:date>
    </item>
    <item>
      <title>I'm on Ubuntu 12.04, x86-64,</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/Unable-to-ative-the-SSE-nstruction-set-byadding-compile-flag/m-p/987284#M4765</link>
      <description>&lt;P&gt;I'm on Ubuntu 12.04, x86-64, gcc 4.6.3, Sandy Bridge CPU. Your command works as expected on my setup, all -msse* and -mavx are enabled. Could you also try the following command:&lt;/P&gt;
&lt;P&gt;gcc -march=native -dM -E - &amp;lt;&amp;lt;&amp;lt;'' | grep SSE&lt;/P&gt;
&lt;P&gt;This will display the predefined macros that indicate the support for various SSE versions. If that doesn't show anything, take a look at /proc/cpuinfo - are the extensions you're looking for there?&lt;/P&gt;
&lt;P&gt;Also, are you by any chance running on a virtual machine? Hypervisors often disable CPU extensions for guest systems.&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;</description>
      <pubDate>Mon, 09 Sep 2013 07:37:49 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/Unable-to-ative-the-SSE-nstruction-set-byadding-compile-flag/m-p/987284#M4765</guid>
      <dc:creator>andysem</dc:creator>
      <dc:date>2013-09-09T07:37:49Z</dc:date>
    </item>
    <item>
      <title>Please verify if ???intrin.h</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/Unable-to-ative-the-SSE-nstruction-set-byadding-compile-flag/m-p/987285#M4766</link>
      <description>Please verify if &lt;STRONG&gt;???intrin.h&lt;/STRONG&gt; header files exist in &lt;STRONG&gt;../4.6.3/include&lt;/STRONG&gt; folder.</description>
      <pubDate>Mon, 09 Sep 2013 12:59:24 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/Unable-to-ative-the-SSE-nstruction-set-byadding-compile-flag/m-p/987285#M4766</guid>
      <dc:creator>SergeyKostrov</dc:creator>
      <dc:date>2013-09-09T12:59:24Z</dc:date>
    </item>
    <item>
      <title>Thank you all above:</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/Unable-to-ative-the-SSE-nstruction-set-byadding-compile-flag/m-p/987286#M4767</link>
      <description>&lt;P&gt;Thank you all above:&lt;/P&gt;
&lt;P&gt;I think it's a “information prompting” bug of gcc on my environment, meaning the information retunred by the command "gcc -march=native -Q--help=target -v" is not correct with reality, because in fact I can use sse ISA without any flags with gcc.&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;</description>
      <pubDate>Mon, 09 Sep 2013 18:44:27 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/Unable-to-ative-the-SSE-nstruction-set-byadding-compile-flag/m-p/987286#M4767</guid>
      <dc:creator>Chenjie_Y_</dc:creator>
      <dc:date>2013-09-09T18:44:27Z</dc:date>
    </item>
    <item>
      <title>Quote:Chenjie Y. wrote:</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/Unable-to-ative-the-SSE-nstruction-set-byadding-compile-flag/m-p/987287#M4768</link>
      <description>&lt;P&gt;&lt;/P&gt;&lt;BLOCKQUOTE&gt;Chenjie Y. wrote:&lt;BR /&gt;&lt;P&gt;&lt;/P&gt;
&lt;P&gt;Thank you all above:&lt;/P&gt;
&lt;P&gt;I think it's a “information prompting” bug of gcc on my environment, meaning the information retunred by the command "gcc -march=native -Q--help=target -v" is not correct with reality, because in fact I can use sse ISA without any flags with gcc.&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;&lt;/P&gt;
&lt;P&gt;All 64-bit versions of gcc for core2 will use sse and sse2 by default.&lt;/P&gt;</description>
      <pubDate>Mon, 09 Sep 2013 19:46:17 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/Unable-to-ative-the-SSE-nstruction-set-byadding-compile-flag/m-p/987287#M4768</guid>
      <dc:creator>TimP</dc:creator>
      <dc:date>2013-09-09T19:46:17Z</dc:date>
    </item>
    <item>
      <title>Last week I integrated GCC</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/Unable-to-ative-the-SSE-nstruction-set-byadding-compile-flag/m-p/987288#M4769</link>
      <description>Last week I integrated GCC version 4.8.1 ( MinGW for Windows ). After my initial verifications I did not see any issues with SSE, SSE2, SSE4.x and AVX Intel instruction sets.</description>
      <pubDate>Mon, 23 Sep 2013 05:34:23 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/Unable-to-ative-the-SSE-nstruction-set-byadding-compile-flag/m-p/987288#M4769</guid>
      <dc:creator>SergeyKostrov</dc:creator>
      <dc:date>2013-09-23T05:34:23Z</dc:date>
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